Electronic component and manufacturing method thereof

ABSTRACT

An electronic component includes a substrate which has a first major surface on one side and a second major surface on the other side, a chip which has a mounting surface on one side and a non-mounting surface on the other side and is disposed on the first major surface of the substrate in a posture that the mounting surface faces the first major surface of the substrate, a sealing insulation layer which seals the chip so as to expose the non-mounting surface above the first major surface of the substrate, and a cover layer which covers the non-mounting surface of the chip.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority to Japanese PatentApplication No. 2018-074077 filed on Apr. 6, 2018, and Japanese PatentApplication No. 2018-074078 filed on Apr. 6, 2018. The entire contentsof these applications are hereby incorporated herein by reference.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to an electronic component and amanufacturing method thereof.

2. Description of the Related Art

Chips to be mounted on mounting substrates include a chip that isconstituted of a monofunctional device or a chip that is constituted ofa composite functional device. Examples of such a monofunctional deviceinclude a resistor, a capacitor, a coil, a diode, a transistor andothers. The composite functional device is constituted with acombination of a plurality of monofunctional devices.

A wiring layout of the mounting substrate is ordinarily set on the basisof an electrode pitch of a chip. However, for convenience of the wiringlayout, there is a case in which a wiring pitch of the mountingsubstrate is necessarily set greater than the electrode pitch of thechip. In this case, the chip is mounted on the mounting substratethrough a pitch conversion substrate which is called an interposer.

JP2013-197263 discloses an example of an electronic component having astructure in which a chip is disposed on a pitch conversion substrate.The electronic component includes a wiring body (substrate) having onesurface and the other surface, an external terminal formed on onesurface of the wiring body, a semiconductor chip disposed on the othersurface of the wiring body and a sealing resin for sealing thesemiconductor chip on the other surface of the wiring body.

SUMMARY OF THE INVENTION

One preferred embodiment of the present invention provides an electroniccomponent including a substrate which has a first major surface on oneside and a second major surface on the other side, a chip which has amounting surface on one side and a non-mounting surface on the otherside and which is disposed on the first major surface of the substratein a posture that the mounting surface faces the first major surface ofthe substrate, a sealing insulation layer which seals the chip so as toexpose the non-mounting surface above the first major surface of thesubstrate, and a cover layer which covers the non-mounting surface ofthe chip.

One preferred embodiment of the present invention provides a method formanufacturing an electronic component including a step of preparing abase substrate that has a first major surface on one side and a secondmajor surface on the other side, a step of preparing a chip that has amounting surface on one side and a non-mounting surface on the otherside, a step of setting a component region corresponding to theelectronic component on the first major surface and disposing the chipat the component region in a posture that the mounting surface faces thefirst major surface, a step of sealing the chip on the first majorsurface by a sealing insulation layer, thereby forming a sealingstructure that includes the base substrate, the chip and the sealinginsulation layer, a step of grinding the sealing structure together withthe chip from the non-mounting surface-side of the chip, therebythinning the sealing structure, a step of forming a cover layer whichcovers the non-mounting surface of the chip, and a dicing step ofcutting the sealing structure along the component region.

The aforementioned or other objects, features, and effects of thepresent invention will be clarified by the following description ofpreferred embodiments given below with reference to the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view which shows an electronic componentaccording to a first preferred embodiment of the present invention.

FIG. 2 is a plan view which shows an internal structure of theelectronic component shown in FIG. 1.

FIG. 3 is a cross-sectional view which is taken along line III-III shownin FIG. 2.

FIG. 4 is an enlarged view of a region IV shown in FIG. 3.

FIG. 5A to FIG. 5M are cross-sectional views showing various processsteps in an example of a method for manufacturing the electroniccomponent shown in FIG. 1.

FIG. 6 is a perspective view which shows an electronic componentaccording to a second preferred embodiment of the present invention.

FIG. 7 is a plan view which shows an internal structure of theelectronic component shown in FIG. 6.

FIG. 8 is a cross-sectional view which is taken along line VIII-VIIIshown in FIG. 7.

FIG. 9 is an enlarged view of a region IX shown in FIG. 8.

FIG. 10 is a plan view which shows an internal structure of anelectronic component according to a third preferred embodiment of thepresent invention.

FIG. 11 is a cross-sectional view which is taken along line of XI-XIshown in FIG. 10.

FIG. 12 is a cross-sectional view which shows an electronic componentaccording to a fourth preferred embodiment of the present invention.

FIG. 13 is a cross-sectional view which shows a first modified exampleof an external electrode layer of the electronic component shown in FIG.1.

FIG. 14 is a cross-sectional view which shows a second modified exampleof an external electrode layer of the electronic component shown in FIG.1.

FIG. 15 is a cross-sectional view which shows a modified example of anexternal electrode layer of the electronic component shown in FIG. 6.

FIG. 16 is a plan view which shows a wiring structure body according toa fifth preferred embodiment of the present invention.

FIG. 17 is a cross-sectional view which is taken along line XVII-XVIIshown in FIG. 16.

FIG. 18A to FIG. 18I are cross-sectional views showing various processsteps in an example of a method for manufacturing the wiring structurebody shown in FIG. 16.

FIG. 19 is a plan view which shows a wiring structure body according toa sixth preferred embodiment of the present invention.

FIG. 20 is a cross-sectional view which is taken along line XX-XX shownin FIG. 19.

FIG. 21A to FIG. 21F are cross-sectional views showing various processsteps in an example of a method for manufacturing the wiring structurebody shown in FIG. 19.

FIG. 22 is a cross-sectional view which shows a wiring structure bodyaccording to a seventh preferred embodiment of the present invention.

FIG. 23 is a plan view which shows a wiring structure body according toan eighth preferred embodiment of the present invention.

FIG. 24 is a cross-sectional view which is taken along line XXIV-XXIVshown in FIG. 23.

FIG. 25A to FIG. 25E are cross-sectional views showing various processsteps in an example of a method for manufacturing the wiring structurebody shown in FIG. 23.

FIG. 26 is a plan view which shows a wiring structure body according toa ninth preferred embodiment of the present invention.

FIG. 27 is a cross-sectional view which is taken along line ofXXVII-XXVII shown in FIG. 26.

FIG. 28A to FIG. 28F are cross-sectional views showing various processsteps in an example of a method for manufacturing the wiring structurebody shown in FIG. 26.

FIG. 29 is a cross-sectional view which shows a wiring structure bodyaccording to a tenth preferred embodiment of the present invention.

FIG. 30 is a plan view which shows an electronic component according toan eleventh preferred embodiment of the present invention.

FIG. 31 is a cross-sectional view which is taken along line XXXI-XXXIshown in FIG. 30.

FIG. 32 is a plan view which shows an electronic component according toa twelfth preferred embodiment of the present invention.

FIG. 33 is a cross-sectional view which is taken along lineXXXIII-XXXIII shown in FIG. 32.

FIG. 34 is a plan view which shows an electronic component according toa thirteenth preferred embodiment of the present invention.

FIG. 35 is a cross-sectional view which is taken along line XXXV-XXXVshown in FIG. 34.

FIG. 36 is a cross-sectional view of a region corresponding to thatshown in FIG. 31 and is a cross-sectional view which shows an electroniccomponent according to a fourteenth preferred embodiment of the presentinvention.

FIG. 37 is a cross-sectional view of a region corresponding to thatshown in FIG. 31 and is a cross-sectional view which shows an electroniccomponent according to a fifteenth preferred embodiment of the presentinvention.

FIG. 38 is a cross-sectional view of a region corresponding to thatshown in FIG. 33 and is a cross-sectional view which shows an electroniccomponent according to a sixteenth preferred embodiment of the presentinvention.

FIG. 39 is a cross-sectional view of a region corresponding to thatshown in FIG. 33 and is a cross-sectional view which shows an electroniccomponent according to a seventeenth preferred embodiment of the presentinvention.

FIG. 40 is a cross-sectional view of a region corresponding to thatshown in FIG. 35 and is a cross-sectional view which shows an electroniccomponent according to an eighteenth preferred embodiment of the presentinvention.

FIG. 41 is a cross-sectional view of a region corresponding to thatshown in FIG. 35 and is a cross-sectional view which shows an electroniccomponent according to a nineteenth preferred embodiment of the presentinvention.

FIG. 42 is a plan view of a region corresponding to that shown in FIG.32 and is a plan view which shows an electronic component according to atwentieth preferred embodiment of the present invention.

FIG. 43 is a plan view of a region corresponding to that shown in FIG.42 and is a plan view which shows an electronic component according to atwenty-first preferred embodiment of the present invention.

FIG. 44 is a cross-sectional view which shows a first modified exampleof a bump structure shown in FIG. 17.

FIG. 45 is a cross-sectional view which shows a second modified exampleof the bump structure shown in FIG. 17.

FIG. 46 is a cross-sectional view which shows a third modified exampleof the bump structure shown in FIG. 17.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the electronic component disclosed in JP2013-197263, the chipdisposed on the substrate is merely sealed by the sealing resin. In thiscase, the size of the electronic component is determined by the size ofthe substrate and the size of the chip and, therefore, the demand fordownsizing cannot be satisfactorily met.

Thus, one preferred embodiment of the present invention provides anelectronic component which can be downsized and a method formanufacturing such an electronic component.

One preferred embodiment of the present invention provides an electroniccomponent including a substrate which has a first major surface on oneside and a second major surface on the other side, a chip which has amounting surface on one side and a non-mounting surface on the otherside and which is disposed on the first major surface of the substratein a posture that the mounting surface faces the first major surface ofthe substrate, a sealing insulation layer which seals the chip so as toexpose the non-mounting surface above the first major surface of thesubstrate, and a cover layer which covers the non-mounting surface ofthe chip.

According to the electronic component, the sealing insulation layer isthinned to such an extent that the non-mounting surface of the chip isexposed from the sealing insulation layer. Thereby, the sealinginsulation layer can be reduced in thickness. On the other hand, thenon-mounting surface of the chip is covered with the cover layer.Thereby, the chip can be protected appropriately. Thus, it is possibleto appropriately downsize the electronic component.

One preferred embodiment of the present invention provides a method formanufacturing an electronic component including a step of preparing abase substrate that has a first major surface on one side and a secondmajor surface on the other side, a step of preparing a chip that has amounting surface on one side and a non-mounting surface on the otherside, a step of setting a component region corresponding to theelectronic component on the first major surface and disposing the chipat the component region in a posture that the mounting surface faces thefirst major surface, a step of sealing the chip on the first majorsurface by a sealing insulation layer, thereby forming a sealingstructure which includes the base substrate, the chip and the sealinginsulation layer, a step of grinding the sealing structure together withthe chip from the non-mounting surface-side of the chip, therebythinning the sealing structure, a step of forming a cover layer whichcovers the non-mounting surface of the chip, and a dicing step ofcutting the sealing structure along the component region.

According to the manufacturing method, in the step of thinning thesealing structure, the sealing insulation layer is ground to such anextent that the non-mounting surface of the chip is exposed. Thereby,the sealing structure can be reduced in thickness. Since the chip isground in a state of being sealed in the sealing insulation layer in thestep of thinning the sealing structure, it is possible to prevent damageof the chip resulting from the grinding. Further, the non-mountingsurface of the chip is covered with the cover layer in the subsequentstep. Thereby, the chip can be protected appropriately. Thus, it ispossible to appropriately downsize the electronic component.

Hereinafter, preferred embodiments of the present invention will bedescribed in detail with reference to the attached drawings.

FIG. 1 is a perspective view which shows an electronic component 1according to the first preferred embodiment of the present invention.FIG. 2 is a plan view which shows an internal structure of theelectronic component 1 shown in FIG. 1. FIG. 3 is a cross-sectional viewwhich is taken along line III-III shown in FIG. 2. FIG. 4 is an enlargedview of a region IV shown in FIG. 3.

The electronic component 1 includes an interposer 2 as a pitchconversion substrate. The interposer 2 has a first major surface 3 onone side, a second major surface 4 on the other side, and a side surface5 which connects the first major surface 3 and the second major surface4.

The first major surface 3 and the second major surface 4 of theinterposer 2 are each formed in a quadrangle shape (in a rectangularshape in the preferred embodiment) in a plan view taken from theirnormal directions (hereinafter, simply referred to as “plan view”). Arecess portion 6 which is recessed toward the second major surface 4 isformed on the first major surface 3. The second major surface 4 isformed in a flat shape.

The recess portion 6 is formed at a center portion of the first majorsurface 3 to be spaced from a peripheral edge of the interposer 2. Therecess portion 6 is formed in a quadrangle shape which has four sidessubstantially parallel to the respective four sides of the interposer 2in plan view. The recess portion 6 may be formed in a polygonal shapeother than a quadrangle shape such as a triangular shape and a hexagonalshape in plan view. The recess portion 6 may be formed in a circularshape or an elliptical shape in plan view.

On the first major surface 3, there is formed a low region 7, a highregion 8 and a connection portion 9 by the recess portion 6. The lowregion 7 is made up of a bottom portion of the recess portion 6. Thehigh region 8 is made up of a region around the recess portion 6. Theconnection portion 9 connects the low region 7 and the high region 8.

The low region 7 is formed in a quadrangle shape which has four sidessubstantially parallel to the respective four sides of the interposer 2in plan view. The high region 8 is formed in a quadrangular annularshape which surrounds the recess portion 6 in plan view. The connectionportion 9 has an inclined surface which is inclined downward from thehigh region 8 to the low region 7. That is, the recess portion 6 isformed in a tapered shape in which an opening is reduced in width fromthe high region 8 to the low region 7 in a cross-sectional view.

The interposer 2 may include a semiconductor material. The interposer 2may include at least any one of silicon, a nitride semiconductormaterial (for example, gallium nitride) and an oxide semiconductormaterial (for example, gallium oxide) as an example of the semiconductormaterial. The interposer 2 includes silicon in the preferred embodiment.

The electronic component 1 includes a major surface insulation layer 11which is formed in a film shape on the first major surface 3. The majorsurface insulation layer 11 may include an inorganic insulatingmaterial. The major surface insulation layer 11 may include at least anyone of silicon oxide, silicon nitride, silicon oxynitride, aluminumoxide, aluminum nitride, and aluminum oxynitride.

The electronic component 1 includes a plurality of wiring layers 12(four layers in the preferred embodiment) which are formed on the majorsurface insulation layer 11. The plurality of wiring layers 12 are eachformed so as to cross the connection portion 9 and extend between thelow region 7 and the high region 8. The plurality of wiring layers 12each include a first pad region 13, a second pad region 14 and a wiringregion 15.

In the preferred embodiment, the plurality of first pad regions 13 areformed one each at each of the four corners of the low region 7. Thefirst pad regions 13 are each formed in a quadrangle shape in plan view.In the preferred embodiment, the plurality of second pad regions 14 areformed one each at each of the four corners of the high region 8. Thesecond pad regions 14 are each formed in a quadrangle shape in planview.

The plurality of wiring regions 15 each connect the first pad region 13and the second pad region 14 which correspond thereto. The wiring region15 is drawn around in a line shape at a region between the low region 7and the high region 8 so as to cross the connection portion 9. Thewiring region 15 may be drawn around in any mode.

In the preferred embodiment, each of the wiring layers 12 has astacked-layer structure which includes a first electrode layer 16 and asecond electrode layer 17 stacked in this order from the side of thefirst major surface 3. The first electrode layer 16 may be a seed layer.The second electrode layer 17 may be a plating layer.

In the preferred embodiment, the first electrode layer 16 has astacked-layer structure which includes a titanium layer 18 and a copperlayer 19 stacked in this order from the side of the first major surface3. In the preferred embodiment, the second electrode layer 17 has asingle layer structure which includes a copper layer (more specifically,a copper plating layer). The second electrode layer 17 may be formedintegrally with the copper layer 19 of the first electrode layer 16. Thesecond electrode layer 17 is greater in thickness than the firstelectrode layer 16. The wiring layer 12 is reduced in resistance valueby the second electrode layer 17.

The electronic component 1 includes a chip 21 which is disposed on thefirst major surface 3. The chip 21 is disposed inside the recess portion6. The chip 21 includes a chip main body 22 formed in a rectangularparallelepiped shape. The chip main body 22 has a mounting surface 23 onone side, a non-mounting surface 24 on the other side, and a chip sidesurface 25 which connects the mounting surface 23 and the non-mountingsurface 24. The non-mounting surface 24 is free of an electrode. Thenon-mounting surface 24 is made up of a ground surface.

The thickness of the chip 21 may be 50 μm or more and 1000 μm or less.The thickness of the chip 21 may be 50 μm or more and 100 μm or less,from 100 μm or more and 200 μm or less, from 200 μm or more and 400 μmor less, from 400 μm or more and 600 μm or less, from 600 μm or more and800 μm or less, or from 800 μm or more and 1000 μm or less.

The chip main body 22 may include at least any one of silicon, a nitridesemiconductor material (for example, gallium nitride), an oxidesemiconductor material (for example, gallium oxide), glass and ceramic.The chip main body 22 includes a functional device. The functionaldevice may be formed on the side of the mounting surface 23. Thefunctional device may include at least anyone of a resistor, acapacitor, a coil, a diode and a transistor.

The chip 21 may include a monofunctional device or a compositefunctional device. The composite functional device is constituted with acombination of the plurality of monofunctional devices. The chip 21 maybe a discrete device or an IC (Integrated Circuit) device.

The chip 21 includes a plurality of terminal electrodes 26 (four in thepreferred embodiment) which are formed on the mounting surface 23. Theplurality of terminal electrodes 26 are electrically connected to thefunctional device. The chip 21 may include an insulation layer whichcovers the mounting surface 23. On the insulation layer, there may beformed a wiring (wiring layer) which is electrically connected to theterminal electrode 26 and the functional device. In this case, theplurality of terminal electrodes 26 may protrude outside from theinsulation layer.

The chip 21 is disposed over the first major surface 3 in a posture thatthe mounting surface 23 faces the interposer 2. The chip 21 is disposedover the low region 7. The plurality of terminal electrodes 26 are eachbonded to the first pad region 13 of the wiring layer 12 through anelectroconductive bonding material 27. The electroconductive bondingmaterial 27 may include solder or metallic paste.

The mounting surface 23 of the chip 21 is positioned at a region betweenthe low region 7 and the high region 8. The non-mounting surface 24 ofthe chip 21 protrudes above the high region 8. The mounting surface 23and the non-mounting surface 24 have an area less than an area of thelow region 7 in plan view. The entirety of the mounting surface 23 facesthe low region 7. That is, the chip 21 is positioned inside a regionsurrounded by a peripheral edge of the low region 7.

The mounting surface 23 and the non-mounting surface 24 may have an arealarger than an area of the low region 7 in plan view. In this case, themounting surface 23 may face a portion of the low region 7 and a portionof the connection portion 9.

The electronic component 1 includes a plurality of electrode bodies 31which are individually formed on the plurality of second pad regions 14.The plurality of electrode bodies 31 are formed on the correspondingsecond pad regions 14 in a one-to-one correspondence relationship. Theplurality of electrode bodies 31 are formed in a block shape or a pillarshape.

The plurality of electrode bodies 31 each have a single layer structurewhich includes a copper layer (more specifically, a copper platinglayer). The plurality of electrode bodies 31 each have a first electrodesurface 32 on one side, a second electrode surface 33 on the other side,and an electrode side surface 34 which connects the first electrodesurface 32 and the second electrode surface 33. The first electrodesurfaces 32 of the plurality of electrode bodies 31 are each bonded to acorresponding second pad region 14. The second electrode surfaces 33 ofthe plurality of electrode bodies 31 are each made up of a groundsurface.

The electronic component 1 includes a sealing insulation layer 41 whichseals the chip 21 on the first major surface 3. The sealing insulationlayer 41 includes an organic insulating material. The sealing insulationlayer 41 may be made up of a sealing resin. The sealing insulation layer41 may include a negative type or a positive type photosensitive resin.The sealing insulation layer 41 may include at least anyone of an epoxyresin, a polyimide resin, a polyamide resin, a polybenzoxazole resin,and an acrylic resin.

The sealing insulation layer 41 seals the chip 21 so as to expose thenon-mounting surface 24 of the chip 21. The sealing insulation layer 41also seals the plurality of electrode bodies 31 so as to expose thesecond electrode surfaces 33 of the plurality of electrode bodies 31.The sealing insulation layer 41 exposes the entirety of the non-mountingsurface 24 and the entirety of the second electrode surfaces 33. Thesealing insulation layer 41 fills a space between the low region 7 andthe mounting surface 23 of the chip 21, and covers the entirety of thechip side surface 25 and the entirety of the electrode side surfaces 34.

The sealing insulation layer 41 includes a sealing major surface 42 anda sealing side surface 43. The sealing major surface 42 faces the firstmajor surface 3 of the interposer 2. More specifically, the sealingmajor surface 42 is formed so as to be substantially parallel to thefirst major surface 3.

The sealing major surface 42 is connected to the non-mounting surface 24of the chip 21 without any difference in level. The sealing majorsurface 42 has a flat surface which extends continuously from thenon-mounting surface 24. That is, the sealing insulation layer 41 has anouter surface which is formed so as to be flush with the non-mountingsurface 24. The sealing major surface 42 forms one ground surface withthe non-mounting surface 24.

The sealing major surface 42 is connected to the second electrodesurfaces 33 of the plurality of electrode bodies 31 without anydifference in level. The sealing major surface 42 has a flat surfacewhich extends continuously from the plurality of second electrodesurfaces 33. That is, the sealing insulation layer 41 has an outersurface which is formed so as to be flush with the plurality of secondelectrode surfaces 33. The sealing major surface 42 forms one groundsurface with the plurality of second electrode surfaces 33.

That is, the sealing major surface 42 forms one flat surface with thenon-mounting surface 24 and the plurality of second electrode surfaces33. The flat surface is made up of a ground surface and formed so as tobe substantially parallel to the second major surface 4 of theinterposer 2.

The sealing side surface 43 extends toward the interposer 2 from aperipheral edge of the sealing major surface 42. The sealing sidesurface 43 is connected to the side surface 5 of the interposer 2without any difference in level. The sealing side surface 43 is formedto be flush with the side surface 5 of the interposer 2.

The electronic component 1 includes a cover layer 46 which covers thenon-mounting surface 24 of the chip 21 on the sealing major surface 42.The cover layer 46 exposes a peripheral edge portion of the sealingmajor surface 42. More specifically, the cover layer 46 includes acovering portion 47 and an extension portion 48.

The covering portion 47 covers the entirety of the non-mounting surface24 of the chip 21. The extension portion 48 is drawn out onto thesealing major surface 42 from the covering portion 47. The extensionportion 48 is drawn out up to a region which is close to the peripheraledge (sealing side surface 43) of the sealing major surface 42. That is,the extension portion 48 is formed to be spaced inwardly from theperipheral edge (sealing side surface 43) of the sealing major surface42. An exposed portion which is exposed from the cover layer 46 in thesealing major surface 42 is formed in an annular shape (morespecifically, in a quadrangular annular shape) so as to surround thecover layer 46 in plan view.

Further, the cover layer 46 includes a cover major surface 49 and acover side surface 50. The cover major surface 49 is formed so as to besubstantially parallel to the non-mounting surface 24 of the chip 21.The cover side surface 50 is positioned at a region that is spacedinwardly from the sealing side surface 43 in plan view. Thereby, a stepportion 51 is formed at a region between the cover side surface 50 andthe sealing side surface 43.

The step portion 51 is formed so as to surround the cover layer 46 (morespecifically, in a quadrangular annular shape) in plan view. Withreference to FIG. 4, a width WS of the step portion 51 may be 1 μm ormore under conditions that the non-mounting surface 24 of the chip 21 iscovered entirely. The width WS is a width in a direction which isorthogonal to a direction in which the step portion 51 extends. Thewidth WS is preferably 10 μm or more.

The thickness of the cover layer 46 is less than that of the sealinginsulation layer 41. The thickness of the cover layer 46 is less thanthat of the chip 21. The thickness of the cover layer 46 may be equal toone-half or less than that of the chip 21. The thickness of the coverlayer 46 may be less than one-half of that of the chip 21. The thicknessof the cover layer 46 may be equal to one-fourth or less than that ofthe chip 21. The thickness of the cover layer 46 may be less thanone-fourth of that of chip 21. The thickness of the cover layer 46 maybe equal to one-hundredth or more than that of the chip 21. Thethickness of the cover layer 46 may be equal to one-thousandth or morethan that of the chip 21.

The thickness of the cover layer 46 may be 1 μm or more and 50 μm orless. The thickness of the cover layer 46 may be 1 μm or more and 2 μmor less, from 2 μm or more and 4 μm or less, from 4 μm or more and 6 μmor less, from 6 μm or more and 8 μm or less, or from 8 μm or more and 10μm or less. The thickness of the cover layer 46 may be 1 μm or more and10 μm or less, from 10 μm or more and 20 μm or less, from 20 μm or moreand 30 μm or less, from 30 μm or more and 40 μm or less, or from 40 μmor more and 50 μm or less.

The cover layer 46 may have a single layer structure made up of a singleinsulating material layer. The cover layer 46 may have a stacked-layerstructure in which a plurality of insulating material layers arestacked. The cover layer 46 may include an organic insulating materialand/or an inorganic insulating material.

The cover layer 46 may have a negative type or a positive typephotosensitive resin as an example of the organic insulating material.The cover layer 46 may include at least any one of an epoxy resin, apolyimide resin, a polyamide resin, a polybenzoxazole resin and anacrylic resin. The cover layer 46 may include at least any one ofsilicon oxide, silicon nitride, silicon oxynitride, aluminum oxide,aluminum nitride and aluminum oxynitride as an example of the inorganicinsulating material.

A plurality of openings 55 (four in the preferred embodiment) are formedin the cover layer 46. The plurality of openings 55 expose individuallythe corresponding second electrode surfaces 33 of the electrode bodies31.

The electronic component 1 includes a plurality of external electrodelayers 56 which are electrically connected to the plurality of electrodebodies 31. The plurality of external electrode layers 56 are connectedto the second electrode surfaces 33 of the electrode bodies 31 insidethe corresponding openings 55. Each of the external electrode layers 56protrudes above the cover major surface 49. Each of the externalelectrode layers 56 includes an overlap portion which covers the covermajor surface 49.

With reference to FIG. 4, the plurality of external electrode layers 56each have a stacked-layer structure which includes a plurality ofelectrode layers. In the preferred embodiment, the plurality of externalelectrode layers 56 each have a stacked-layer structure including an Nilayer 57, a Pd layer 58 and an Au layer 59 which are stacked in thisorder from the second electrode surface 33-side of the electrode body31.

The Ni layer 57 is connected to the second electrode surface 33 of theelectrode body 31 inside the opening 55. The Ni layer 57 protrudes abovethe cover major surface 49. The Ni layer 57 has an overlap portion whichcovers the cover major surface 49.

The Pd layer 58 covers an outer surface of the Ni layer 57 on the covermajor surface 49. The thickness of the Pd layer 58 is less than that ofthe Ni layer 57. The Au layer 59 covers an outer surface of the Pd layer58 on the cover major surface 49. The thickness of the Au layer 59 isless than that of the Ni layer 57.

As described so far, according to the electronic component 1, thesealing insulation layer 41 is thinned to such an extent that thenon-mounting surface 24 of the chip 21 is exposed from the sealinginsulation layer 41. Thereby, the sealing insulation layer 41 can bereduced in thickness. On the other hand, the non-mounting surface 24 ofthe chip 21 is covered with the cover layer 46. Thereby, the chip 21 canbe protected appropriately. Thus, it is possible to appropriatelydownsize the electronic component 1.

FIG. 5A to FIG. 5M are cross-sectional views showing various processsteps in an example of a method for manufacturing the electroniccomponent 1 shown in FIG. 1.

With reference to FIG. 5A, a base substrate 62 is prepared. The basesubstrate 62 serves as a base of the interposer 2. The base substrate 62may be a silicon wafer in a disk shape. The base substrate 62 has afirst major surface 63 on one side and a second major surface 64 on theother side. The first major surface 63 and the second major surface 64of the base substrate 62 correspond respectively to the first majorsurface 3 and the second major surface 4 of the interposer 2.

Then, a plurality of component regions 65 and a boundary region 66 areset in the first major surface 63 of the base substrate 62. Theplurality of component regions 65 are each a region in which theelectronic component 1 is formed. The plurality of component regions 65may be set in a matrix shape in plan view. The boundary region 66 is aregion which demarcates the plurality of component regions 65. Theboundary region 66 may be set in a lattice shape. The boundary region 66is given as a dicing line.

Then, with reference to FIG. 5B, at each of the component regions 65,the recess portion 6 is formed in the first major surface 63 of the basesubstrate 62. The recess portion 6 is formed by selectively digging downthe first major surface 63, for example, by etching through a mask (notshown).

Then, the major surface insulation layer 11 is formed on the first majorsurface 63 of the base substrate 62. The major surface insulation layer11 may be formed by a CVD (Chemical Vapor Deposition) method or thermaloxidation treatment. The major surface insulation layer 11 may be asilicon oxide film.

Then, with reference to FIG. 5C, the plurality of wiring layers 12 areformed on the major surface insulation layer 11. In this step, the firstelectrode layer 16 is first formed on the entire front surface of themajor surface insulation layer 11. The step of forming the firstelectrode layer 16 includes a step of forming a titanium layer 18 and acopper layer 19 in this order from the side of the major surfaceinsulation layer 11. The titanium layer 18 and the copper layer 19 maybe each formed by a sputtering method. The titanium layer 18 and thecopper layer 19 are each formed as a seed layer.

Then, a mask (not shown) having a predetermined pattern is formed on thefirst electrode layer 16. The mask (not shown) has a plurality ofopenings which expose a region at which a plurality of second electrodelayers 17 are to be formed in the first electrode layer 16.

Then, the plurality of second electrode layers 17 are formed on thefirst electrode layer 16. The plurality of second electrode layers 17are formed on a portion which is exposed from the plurality of openingsof the mask (not shown) in the first electrode layer 16. The secondelectrode layer 17 may be formed by an electrolytic copper platingmethod. The mask (not shown) is removed thereafter.

Then, a portion which is exposed from the second electrode layer 17 inthe first electrode layer 16 is removed. An unnecessary portion of thefirst electrode layer 16 may be removed by etching in which the secondelectrode layer 17 is used as a mask. Thereby, a plurality of wiringlayers 12 having a predetermined pattern are formed.

Then, with reference to FIG. 5D, a mask 67 having a predeterminedpattern is formed on the major surface insulation layer 11. The mask 67has a plurality of openings 68 which expose individually the first padregions 13 of the plurality of wiring layers 12.

Then, with reference to FIG. 5E, the plurality of electrode bodies 31are each formed on a corresponding first pad region 13. The plurality ofelectrode bodies 31 may be formed by an electrolytic copper platingmethod.

Then, with reference to FIG. 5F, the mask 67 is removed. Thereby, theplurality of electrode bodies 31 remain in a state that they are erectedon the corresponding first pad regions 13.

Then, with reference to FIG. 5G, the plurality of chips 21 are eachdisposed in a corresponding component region 65. The chips 21 are eachdisposed in each component region 65 in a state that the mountingsurface 23 faces the base substrate 62. The terminal electrode 26 of thechip 21 is bonded to the first pad region 13 of the corresponding wiringlayer 12 through the electroconductive bonding material 27.

Then, with reference to FIG. 5H, the sealing insulation layer 41 isformed on the first major surface 63. The sealing insulation layer 41covers collectively the entirety of the chip 21 and the entirety of theplurality of electrode bodies 31. Thereby, a sealing structure 69 isformed which includes the base substrate 62, the chip 21 and the sealinginsulation layer 41.

Then, with reference to FIG. 5I, the sealing structure 69 is ground fromthe non-mounting surface 24-side of the chip 21. That is, the sealingmajor surface 42 of the sealing insulation layer 41 is ground. Thesealing structure 69 may be ground by a CMP (Chemical MechanicalPolishing) method.

The step of grinding the sealing structure 69 includes a first grindingstep in which the sealing major surface 42 is ground until thenon-mounting surface 24 of the chip 21 and the second electrode surfaces33 of the plurality of electrode bodies 31 are exposed. The step ofgrinding the sealing structure 69 also includes a second grinding stepin which after the first grinding step, the sealing major surface 42 isground continuously, thereby grinding and thinning the chip 21 and theplurality of electrode bodies 31. Thereby, the chip 21 is adjusted forthickness and the electronic component 1 is also adjusted for a finalthickness.

Then, with reference to FIG. 5J, an insulating material layer whichserves as a base of the cover layer 46 is formed on the sealing majorsurface 42 of the sealing structure 69. In the preferred embodiment, aresin layer is formed as an example of the insulating material layer.The resin layer is formed so as to cover substantially the entirety ofthe sealing major surface 42.

The resin layer may be formed by using a photosensitive resin solvent.In this case, the photosensitive resin solvent is coated by a spincoating method on the sealing major surface 42 so as to coversubstantially the entirety of the sealing major surface 42. Thereby, theresin layer is formed.

A resin layer which is made up of a photosensitive resin film may beformed. In this case, the photosensitive resin film is stuck on thesealing major surface 42 so as to cover substantially the entirety ofthe sealing major surface 42. Thereby, the resin layer is formed.

Then, with reference to FIG. 5K, after being photo-exposed in a patterncorresponding to the cover layer 46, the resin layer is developed.Thereby, the cover layer 46 made up of the resin layer is formed. Inthis step, the cover layer 46 is formed which covers the non-mountingsurface 24 of the chip 21 and also has the plurality of openings 55which expose individually the second electrode surfaces 33 of theelectrode bodies 31.

Further, in this step, the cover layer 46 having a peripheral edge at aregion that is spaced inwardly from a peripheral edge of each componentregion 65, in plan view taken in a normal direction to the first majorsurface 63 is formed in each of the component regions 65. A regionbetween mutually adjacent cover layers 46 in the sealing major surface42 is given as a dicing region 70 (dicing street).

The cover layer 46 can be formed also by an insulation layer (not shown)including an inorganic insulating material. In this case, the insulationlayer is formed so as to cover substantially the entirety of the sealingmajor surface 42. The insulation layer may be formed by a CVD method.

Then, a mask (not shown) having a predetermined pattern whichcorresponds to the cover layer 46 is formed on the insulation layer. Themask (not shown) covers a region at which the cover layer 46 is to beformed and has an opening which exposes a region at which a step portion51 and a plurality of openings 55 are to be formed. Then, an unnecessaryportion of the insulation layer is removed by etching through the mask.Thereby, the cover layer 46 having a predetermined pattern is formed.

Then, with reference to FIG. 5L, the plurality of external electrodelayers 56 are each formed inside a corresponding opening 55. The step offorming the external electrode layer 56 includes a step of forming an Nilayer 57, a Pd layer 58 and an Au layer 59 in this order from the secondelectrode surface 33-side of the electrode body 31. The Ni layer 57, thePd layer 58 and the Au layer 59 may be individually formed by anelectroless plating method. Thereby, the external electrode layer 56 isformed.

Then, with reference to FIG. 5M, the sealing structure 69 is cut alongthe dicing region 70 (boundary region 66). The sealing structure 69 iscut by using a dicing blade. Thereby, the plurality of electroniccomponents 1 are cut out. The electronic component 1 is manufactured bythe steps including the above.

As described so far, according to the method for manufacturing theelectronic component 1, in a step of thinning the sealing structure 69(refer to FIG. 5I), the sealing insulation layer 41 is ground until thenon-mounting surface 24 of the chip 21 is exposed. Thereby, the sealingstructure 69 can be reduced in thickness. Further, in the step ofthinning the sealing structure 69, the chip 21 is ground in a state ofbeing sealed in the sealing insulation layer 41 and, therefore, it ispossible to prevent damage of the chip 21 resulting from the grinding.

Further, the non-mounting surface 24 of the chip 21 is covered with thecover layer 46 in a step of forming the cover layer 46 (refer to FIG.5J). Thereby, the chip 21 can be protected appropriately. Thus, it ispossible to appropriately downsize the electronic component 1.

Further, according to the method for manufacturing the electroniccomponent 1, in the step of forming the cover layer 46 (refer to FIG.5J), there is formed the cover layer 46 having a peripheral edge at aregion that is spaced inwardly from a peripheral edge of the componentregion 65. A region between the plurality of cover layers 46 which aremutually adjacent is given as the dicing region 70.

Thereby, in the dicing step (refer to FIG. 5M), there is eliminated anecessity for cutting the cover layer 46, thus making it possible toprevent clogging or deterioration of the dicing blade caused by thecover layer 46. It is, thereby, possible to cut appropriately thesealing insulation layer 41 and also to prevent a deteriorated qualityof the electronic component 1. The above-described structure is inparticular effective in such a case that the cover layer 46 includes aresin layer (organic insulating material).

FIG. 6 is a perspective view which shows an electronic component 71according to the second preferred embodiment of the present invention.FIG. 7 is a plan view which shows an internal structure of theelectronic component 71 shown in FIG. 6. FIG. 8 is a cross-sectionalview which is taken along line VIII-VIII shown in FIG. 7. FIG. 9 is anenlarged view of a region IX shown in FIG. 8. In the following,structures corresponding to the structures in the electronic component 1will be given the same reference signs, and a description thereof isomitted.

A cover layer 46 according to the electronic component 71 is formed onlyat a center portion of a sealing insulation layer 41 in plan view. Thecover layer 46 (covering portion 47) covers the entirety of anon-mounting surface 24 of a chip 21. The cover layer 46 (extensionportion 48) is formed to be spaced toward the side of a recess portion 6from a plurality of external electrode layers 56 in plan view.

The entirety of the cover layer 46 may be positioned inside a regionsurrounded by a peripheral edge of the recess portion 6 in plan view. Acover side surface 50 of the cover layer 46 is positioned at a regionthat is spaced inwardly from a sealing side surface 43 in plan view. Astep portion 51 is formed at a region between the cover side surface 50and the sealing side surface 43 on a sealing major surface 42.

The plurality of external electrode layers 56 are not in contact withthe cover layer 46. The plurality of external electrode layers 56 covera second electrode surface 33 of a corresponding electrode body 31 onthe sealing major surface 42. The plurality of external electrode layers56 may cover a portion of the sealing major surface 42.

With reference to FIG. 9, it is preferable that a thickness TC of thecover layer 46 is equal to or less than a thickness TE of the pluralityof external electrode layers 56 (TCTE). It is more preferable that thethickness TC is less than the thickness TE (TC<TE).

According to the above-described structure, the cover layer 46 can beprevented from being brought into contact with a connection target whenthe electronic component 71 is connected to the connection target.Thereby, it is possible to connect appropriately the plurality ofexternal electrode layers 56 to the connection target. It is alsopossible to prevent probe needles from making contact with the coverlayer 46 when the electronic component 71 is subjected to an electricaltest. Thereby, the probe needles can be appropriately come into contactwith the plurality of external electrode layers 56. Thus, it is possibleto smoothly perform the electrical test. As a matter of course, if noproblem is found, a cover layer 46 that has a thickness TC exceeding thethickness TE of the external electrode layer 56 may be formed (TE<TC).

As described so far, the electronic component 71 is also able to providesubstantially the same technical effects as those described with respectto the electronic component 1. The electronic component 71 can bemanufactured only by changing the layout of a mask for forming the coverlayer 46 in the previously described step of forming the cover layer 46(refer to FIG. 5K).

FIG. 10 is a plan view which shows an internal structure of anelectronic component 81 according to the third preferred embodiment ofthe present invention. FIG. 11 is a cross-sectional view which is takenalong line XI-XI shown in FIG. 10. In the following, structurescorresponding to the structures in the electronic component 1 will begiven the same reference signs, and a description thereof is omitted.

In the preferred embodiment, a plurality of wiring layers 12 eachinclude a third pad region 82 formed at a high region 8. The third padregion 82 is interposed at a portion positioned at the high region 8 ina wiring region 15. That is, the wiring region 15 includes a portionwhich connects a first pad region 13 and the third pad region 82. Thewiring region 15 also includes a portion which connects a second padregion 14 and the third pad region 82.

A chip 21 is disposed at the high region 8 so as to cover a recessportion 6. A terminal electrode 26 of the chip 21 is bonded to the thirdpad region 82 of the corresponding wiring layer 12 through anelectroconductive bonding material 27 at the high region 8. A recessedspace 83 is formed at a region between a mounting surface 23 of the chip21 and the recess portion 6.

The electronic component 81 includes a second chip 84 (lower chip) whichis disposed inside the recess portion 6 (recessed space 83). The secondchip 84 overlaps with the chip 21 in plan view. That is, the second chip84 is disposed three-dimensionally with respect to the chip 21.

The second chip 84 includes a second chip main body 85 formed in arectangular parallelepiped shape. The second chip main body 85 has asecond mounting surface 86 on one side, a second non-mounting surface 87on the other side and a second chip side surface 88 which connects thesecond mounting surface 86 and the second non-mounting surface 87. Thenon-mounting surface 24 is free of an electrode.

The second chip main body 85 may include at least any one of silicon, anitride semiconductor material (for example, gallium nitride), an oxidesemiconductor material (for example, gallium oxide), glass and ceramic.The second chip main body 85 includes a functional device. Thefunctional device may be formed on the side of the second mountingsurface 86. The functional device may include at least any one of aresistor, a capacitor, a coil, a diode and a transistor.

The second chip 84 may include a monofunctional device or a compositefunctional device. The composite functional device is constituted with acombination of the plurality of monofunctional devices. The second chip84 may be a discrete device or an IC (Integrated Circuit) device.

The second chip 84 includes a plurality of second terminal electrodes 89(four in the preferred embodiment) which are formed on the secondmounting surface 86. The plurality of second terminal electrodes 89 areconnected electrically to the functional device. The second chip 84 mayinclude an insulation layer which covers the second mounting surface 86.On the insulation layer, there may be formed a wiring (wiring layer)which is electrically connected to the second terminal electrode 89 andthe functional device. In this case, the plurality of second terminalelectrode 89 may protrude outside from the insulation layer.

The second chip 84 is disposed over a low region 7 in a posture that thesecond mounting surface 86 faces the low region 7. The plurality ofsecond terminal electrodes 89 are each bonded to the first pad region 13of the corresponding wiring layer 12 through an electroconductivebonding material 90. Thereby, the second chip 84 is electricallyconnected to the chip 21 through the wiring layer 12. Theelectroconductive bonding material 90 may include solder or metallicpaste.

The second mounting surface 86 and the second non-mounting surface 87are positioned at a region between the low region 7 and the high region8 of an interposer 2. The second non-mounting surface 87 may protrudeabove the high region 8 of the interposer 2. In this case, the secondnon-mounting surface 87 is positioned at a region between the highregion 8 and the mounting surface 23 of the chip 21.

The second mounting surface 86 and the second non-mounting surface 87have an area which is less than an area of the low region 7 in planview. The entirety of the second mounting surface 86 faces the lowregion 7. That is, the second chip 84 is positioned inside a regionsurrounded by a peripheral edge of the low region 7. The second mountingsurface 86 and the second non-mounting surface 87 may have an area thatexceeds an area of the low region 7 in plan view. The second mountingsurface 86 may face a portion of the low region 7 and a portion of theconnection portion 9.

A sealing insulation layer 41 seals the second chip 84 inside the recessportion 6 (recessed space 83). The sealing insulation layer 41 seals thechip 21 so that the entirety of the non-mounting surface 24 of the chip21 can be exposed outside the recess portion 6 (recessed space 83). Thesealing insulation layer 41 also seals each of electrode bodies 31 sothat the entirety of a second electrode surface 33 of each of theelectrode bodies 31 can be exposed outside the recess portion 6(recessed space 83).

As described so far, the electronic component 81 is also able to providesubstantially the same technical effects as those described previouslywith respect to the electronic component 1. Further, in the electroniccomponent 81, the chip 21 and the second chip 84 are disposedthree-dimensionally on the first major surface 3 of the interposer 2.Thereby, where the electronic component 81 is mounted on a mountingsubstrate, it is possible to mount the chip 21 and the second chip 84three-dimensionally with respect to the mounting substrate.

Therefore, as compared with a case where the chip 21 and the second chip84 are individually mounted on the mounting substrate, it is possible toreduce an area of the mounting substrate which is exclusively occupiedby the chip 21 and the second chip 84. Further, since the chip 21 andthe second chip 84 can be mounted on the mounting substrate by a singlestep, it is possible to prevent a mounting step from being complicated.

The electronic component 81 can be manufactured by executing a step inwhich the chip 21 is disposed at the high region 8 after the second chip84 is disposed at the low region 7 in the previously described step ofdisposing the chip 21 (refer to FIG. 5G).

The step of disposing the second chip 84 includes a step in which thesecond terminal electrode 89 of the second chip 84 is connected to thefirst pad region 13 of the corresponding wiring layer 12. The step ofdisposing the chip 21 includes a step in which a terminal electrode 26of the chip 21 is connected to the third pad region 82 of thecorresponding wiring layer 12. The cover layer 46 according to thepreviously described second preferred embodiment may be adopted in theelectronic component 81.

In the preferred embodiment, a description has been given of a casewhere one second chip 84 is disposed inside the recess portion 6(recessed space 83). However, the plurality of (two or more) secondchips 84 may be disposed inside the recess portion 6 (recessed space83). In this case, the plurality of second chips 84 may be electricallyconnected to each other through the wiring layer 12 or another wiringlayer. The plurality of second chips 84 may also be electricallyconnected to the chip 21 through the wiring layer 12 or another wiringlayer.

FIG. 12 is a cross-sectional view which shows an electronic component 91according to the fourth preferred embodiment of the present invention.In the following, structures corresponding to the structures in theelectronic component 1 will be given the same reference signs, and adescription thereof is omitted.

In the electronic component 91, a first major surface 3 of an interposer2 is made up of a flat surface. That is, no recess portion 6 is formedon the first major surface 3. Thereby, the first major surface 3 and asecond major surface 4 are formed as flat surfaces which aresubstantially parallel to each other.

As described so far, the electronic component 91 is also able to providesubstantially the same technical effects as those described previouslywith respect to the electronic component 1. The electronic component 91can be manufactured by omitting the previously described step of formingthe recess portion 6 (refer to FIG. 5B). Such a structure that the firstmajor surface 3 is made up of a flat surface is also applicable to thepreviously described second preferred embodiment.

A description has been so far given of the first to the fourth preferredembodiments of the present invention. However, the present invention canbe carried out in still other modes.

The external electrode layer 56 according to the previously describedfirst preferred embodiment may have a structure which is shown in FIG.13. FIG. 13 is a cross-sectional view which shows the first modifiedexample of the external electrode layer 56 of the electronic component 1shown in FIG. 1. In the following, structures corresponding to thestructures in the electronic component 1 will be given the samereference signs, and a description thereof is omitted.

With reference to FIG. 13, the entirety of the plurality of externalelectrode layers 56 may be formed individually so as to be housed insidean opening 55. More specifically, the plurality of external electrodelayers 56 may have a front surface which is positioned on the side of asealing insulation layer 41 in relation to a cover major surface 49inside a corresponding opening 55. In this case, an Ni layer 57, a Pdlayer 58 and an Au layer 59 may be in contact with an inner wall surfaceof the corresponding opening 55.

Even the above-described structure is able to provide substantially thesame technical effects as those described previously with respect to theelectronic component 1. The external electrode layer 56 according to thefirst modified example is also applicable to the third preferredembodiment and the fourth preferred embodiment.

The external electrode layer 56 according to previously described firstpreferred embodiment may have a structure shown in FIG. 14. FIG. 14 is across-sectional view which shows the second modified example of theexternal electrode layer 56 of the electronic component 1 shown inFIG. 1. In the following, structures corresponding to the structures inthe electronic component 1 will be given the same reference signs, and adescription thereof is omitted.

With reference to FIG. 14, the plurality of external electrode layers 56may each include a solder layer 95 in place of the stacked-layerstructure which includes the Ni layer 57, the Pd layer 58 and the Aulayer 59. The solder layer 95 may be formed in a hemispherical shape.The solder layer 95 protrudes above the cover major surface 49. Thesolder layer 95 may overlap with the cover major surface 49.

Even the above-described structure is also able to provide substantiallythe same technical effects as those described previously in theelectronic component 1. The external electrode layer 56 according to thesecond modified example is also applicable to the third preferredembodiment and the fourth preferred embodiment.

The external electrode layer 56 according to the previously describedsecond preferred embodiment may have a structure which is shown in FIG.15. FIG. 15 is a cross-sectional view which shows a modified example ofthe external electrode layer 56 of the electronic component 71 shown inFIG. 6. In the following, structures corresponding to the structures inthe electronic component 71 will be given the same reference signs, anda description thereof is omitted.

With reference to FIG. 15, the plurality of external electrode layers 56may each include a solder layer 96 in place of the stacked-layerstructure which includes the Ni layer 57, the Pd layer 58 and the Aulayer 59. The solder layer 96 may be formed in a hemispherical shape.The solder layer 96 may overlap with the sealing major surface 42. Eventhe above-described structure is also able to provide substantially thesame technical effects as those described previously in the electroniccomponent 71.

In the first to the fourth preferred embodiments which have beendescribed previously, a mode may be adopted in which no externalelectrode layer 56 is formed. In this case, the second electrode surface33 of the electrode body 31 may be formed as an external terminal whichis connected externally.

In the previously described first to fourth preferred embodiments, theexternal electrode layer 56 may include a single layer structure or astacked-layer structure which includes at least anyone of the Ni layer57, the Pd layer 58 and the Au layer 59. For example, the externalelectrode layer 56 may have a two-layer structure which includes the Nilayer 57 and the Au layer 59 or may have a single layer structure whichincludes only the Ni layer 57.

The manufacturing method according to the previously described first tofourth preferred embodiments may also include a grinding step ofgrinding the second major surface 64 of the base substrate 62. In thiscase, the second major surface 4 of the interposer 2 is given as aground surface. The step of grinding the base substrate 62 is executedto reduce the thickness of the interposer 2. Therefore, it is possibleto further downsize the electronic components 1, 71, 81 and 91.

The step of grinding the base substrate 62 can be executed at anytiming. The step of grinding the base substrate 62 may be executed priorto the step of forming the major surface insulation layer 11 or may beexecuted prior to the dicing step.

In the previously described first to fourth preferred embodiments, adescription has been given of an example in which the interposer 2 ismade of a semiconductor material (silicon). However, the interposer 2may include an organic insulating material or an inorganic insulatingmaterial in place of the semiconductor material.

In this case, the interposer 2 may include at least any one of an epoxyresin, a polyimide resin, a polyamide resin, a polybenzoxazole resin andan acrylic resin as an example of the organic insulating material.

The interposer 2 may also include at least any one of silicon oxide,silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitrideand aluminum oxynitride as an example of the inorganic insulatingmaterial. Where the interposer 2 is made of an insulating material, themajor surface insulation layer 11 may be removed.

In the previously described first to fourth preferred embodiments, adescription has been given of an example in which the sealing insulationlayer 41 is made up of a sealing resin layer including an organicinsulating material. However, the sealing insulation layer 41 mayinclude an inorganic insulating material in place of the organicinsulating material. The sealing insulation layer 41 may include atleast anyone of silicon oxide, silicon nitride, silicon oxynitride,aluminum oxide, aluminum nitride and aluminum oxynitride as an exampleof the inorganic insulating material.

In the previously described first to fourth preferred embodiments, thefirst major surface 3 of the interposer 2 may be roughened. The firstmajor surface 3 may include an uneven structure as an example of a roughsurface. The roughened first major surface 3 enables increasing anadhesion force of the major surface insulation layer 11, etc., to thefirst major surface 3.

The roughened first major surface 3 can be formed, for example, byroughening the first major surface 63 of the base substrate 62 prior tothe step of forming the major surface insulation layer 11 (also refer toFIG. 5B). The roughening step may include etching, a sandblastingmethod, a laser irradiation method and any other known rougheningmethods.

In the previously described first to fourth preferred embodiments, wherethe electronic components 1, 71, 81 and 91 are manufactured by using asemiconductor material, the property of semiconductor material or amanufacturing method of a semiconductor device, the electroniccomponents 1, 71, 81 and 91 may be each called as “a semiconductordevice”.

The case where they are manufactured by using a semiconductor material,the property of semiconductor material or a manufacturing method of asemiconductor device may include a case that the interposer 2 includes asemiconductor material such as silicon or a case that the chip 21includes a semiconductor device such as a diode and a transistor, or acase that the above described cases are both established.

The present specification shall not restrict any mode of combination ofthe features shown in the first to the fourth preferred embodiments. Thefirst to the fourth preferred embodiments can be combined in any givenform or in any given mode among these embodiments. That is, there may beadopted such a mode that the features shown in the first to the fourthpreferred embodiments are combined in any given form or in any givenmode.

FIG. 16 is a plan view which shows a wiring structure body 101 accordingto the fifth preferred embodiment of the present invention. FIG. 17 is across-sectional view which is taken along line XVII-XVII shown in FIG.16.

With reference to FIG. 16 and FIG. 17, the wiring structure body 101 isa wiring member interposed between a chip component and a connectiontarget when the chip component is bonded to the connection target. InFIG. 16 and FIG. 17, for the convenience of description, there is shownsuch a state that the chip component is not connected to the wiringstructure body 101.

The wiring structure body 101 forms a current path between the chipcomponent and the connection target. The wiring structure body 101transmits an electric signal from the connection target to the chipcomponent and also transmits an electric signal from the chip componentto the connection target. The chip component may include a functionaldevice. The chip component may be a discrete device made up of a singlefunctional device. The chip component may be an integrated circuitdevice provided with multiple functional devices.

The wiring structure body 101 includes a support substrate 102, a baseelectrode layer 103, a wiring layer 104, an insulation layer 105, a bumpstructure 106 and a sealing insulation layer 107. In FIG. 16, aninternal structure of the wiring structure body 101 is shown by seeingthrough the sealing insulation layer 107.

The support substrate 102 has a major surface 108. More specifically,the support substrate 102 includes a base body 109 and a major surfaceinsulation layer 110. The base body 109 may be a semiconductor substrateas well. The semiconductor substrate may include silicon. The majorsurface insulation layer 110 covers a major surface of the base body109. The major surface 108 of the support substrate 102 is formed by themajor surface insulation layer 110. The major surface insulation layer110 may include silicon oxide or silicon nitride.

The base electrode layer 103 is formed in a film shape on the majorsurface 108 of the support substrate 102. The base electrode layer 103may be drawn around in a line shape on the major surface 108. The baseelectrode layer 103 may be drawn around in any mode. In the preferredembodiment, the base electrode layer 103 includes a line-shaped regionand a quadrangle-shaped region in a plan view taken from a normaldirection of the major surface 108 of the support substrate 102(hereinafter, simply referred to as “plan view”). FIG. 16 shows thequadrangle-shaped region of the base electrode layer 103.

The base electrode layer 103 has a stacked-layer structure including afirst electrode layer 111 and a second electrode layer 112 which arestacked in this order from the side of the support substrate 102. A sidesurface of the second electrode layer 112 may be formed so as to beflush with a side surface of the first electrode layer 111. The sidesurface of the second electrode layer 112 may protrude outside inrelation to the side surface of the first electrode layer 111. The sidesurface of the second electrode layer 112 may be formed inside inrelation to the side surface of the first electrode layer 111.

The first electrode layer 111 includes at least one of titanium andchromium. In the preferred embodiment, the first electrode layer 111includes titanium (more specifically, a titanium seed layer). The secondelectrode layer 112 includes at least one of copper and gold. In thepreferred embodiment, the second electrode layer 112 includes copper(more specifically, a copper seed layer).

A total thickness T0 of the base electrode layer 103 may be 0.1 μm ormore and 1.5 μm or less. The total thickness T0 may be 0.1 μm or moreand 0.5 μm or less, from 0.5 μm or more and 1.0 μm or less, or from 1.0μm or more and 1.5 μm or less.

A thickness T1 of the first electrode layer 111 may be 0.05 μm or moreand 0.5 μm or less. The thickness T1 may be 0.05 μm or more and 0.1 μmor less, from 0.1 μm or more and 0.2 μm or less, from 0.2 μm or more and0.3 μm or less, from 0.3 μm or more and 0.4 μm or less, or from 0.4 μmor more and 0.5 μm or less.

A thickness T2 of the second electrode layer 112 may be 0.05 μm or moreand 1.0 μm or less. The thickness T2 may be 0.05 μm or more and 0.1 μmor less, from 0.1 μm or more and 0.5 μm or less, or from 0.5 μm or moreand 1.0 μm or less.

The thickness T1 of the first electrode layer 111 and the thickness T2of the second electrode layer 112 may be combined in the numerical valueranges described above. The thickness T2 of the second electrode layer112 may be equal to or more than the thickness T1 of the first electrodelayer 111 (T1≤T2).

The wiring layer 104 is formed in a film shape on the base electrodelayer 103. The wiring layer 104 has a planar shape corresponding to thebase electrode layer 103 in plan view. In the preferred embodiment, thewiring layer 104 is drawn around in a line shape along the baseelectrode layer 103. The wiring layer 104 includes a line-shaped regionand a quadrangle-shaped region in plan view.

The wiring layer 104 is formed to be spaced inward of the base electrodelayer 103 from a peripheral edge portion of the base electrode layer103, and exposes the peripheral edge portion of the base electrode layer103. A thickness T3 of the wiring layer 104 may be 0.05 μm or more and20 μm or less. The thickness T3 may be 0.05 μm or more and 5 μm or less,from 5 μm or more and 10 μm or less, from 10 μm or more and 15 μm orless, or from 15 μm or more and 20 μm or less.

It is preferable that the thickness T3 of the wiring layer 104 is equalto or more than the total thickness T0 of the base electrode layer 103(T0≤T3). It is more preferable that the thickness T3 exceeds the totalthickness T0 (T0<T3).

The wiring layer 104 includes at least any one of copper, nickel andgold. The wiring layer 104 preferably includes the sameelectroconductive material as that of the second electrode layer 112. Inthe preferred embodiment, the wiring layer 104 includes copper (morespecifically, copper plating layer).

The wiring layer 104 includes a pad portion 113 (connection portion)which is to be connected externally. The pad portion 113 is formed atany given region of the wiring layer 104. FIG. 16 shows an example inwhich the pad portion 113 is formed at the quadrangle-shaped region ofthe wiring layer 104.

The insulation layer 105 is formed on the base electrode layer 103. Theinsulation layer 105 has a planar shape corresponding to a planar shapeof the base electrode layer 103. In the preferred embodiment, theinsulation layer 105 is drawn around in a line shape along the baseelectrode layer 103. The insulation layer 105 includes a line-shapedregion and a quadrangle-shaped region in plan view.

More specifically, the insulation layer 105 is formed in the peripheraledge portion of the base electrode layer 103. The insulation layer 105covers the wiring layer 104 so as to expose the pad portion 113.Thereby, a pad opening 114 for exposing the pad portion 113 of thewiring layer 104 is formed in the insulation layer 105.

The insulation layer 105 protrudes to a region outside the baseelectrode layer 103 from above the peripheral edge portion of the baseelectrode layer 103. The insulation layer 105 protrudes in a transversedirection along a major surface of the base electrode layer 103. Theinsulation layer 105 faces the major surface 108 in a normal directionof the major surface 108 at the region outside the base electrode layer103.

More specifically, the insulation layer 105 includes a base portion 115,a covering portion 116 and a protruding portion 117. The base portion115 is formed on the peripheral edge portion of the base electrode layer103. The covering portion 116 extends from the base portion 115 towardabove the wiring layer 104 and demarcates the pad opening 114.

The protruding portion 117 extends from the base portion 115 in adirection opposite to the wiring layer 104. The protruding portion 117extends in the transverse direction along the major surface of the baseelectrode layer 103 and protrudes to a region outside the base electrodelayer 103. The protruding portion 117 faces the major surface 108 in anormal direction of the major surface 108 at the region outside the baseelectrode layer 103. The protruding portion 117 defines a space 118together with the major surface 108 and a side surface of the baseelectrode layer 103. The space 118 is recessed toward the side of thebase electrode layer 103

A ratio W1/T0, which is a ratio of a width W1 of the protruding portion117 in relation to the total thickness T0 of the base electrode layer103, may be 1 or more and 10 or less. It is preferable that the ratioW1/T0 is 1 or more and 2 or less, from 2 or more and 4 or less, from 4or more and 6 or less, from 6 or more and 8 or less, or 8 or more and 10or less. It is preferable that the ratio W1/T0 is 1 or more and 5 orless.

The width W1 may be 0.05 μm or more and 6.0 μm or less. The width W1 maybe 0.05 μm or more and 1.0 μm or less, from 1.0 μm or more and 2.0 μm orless, from 2.0 μm or more and 3.0 μm or less, from 3.0 μm or more and4.0 μm or less, from 4.0 μm or more and 5.0 μm or less, or from 5.0 μmor more and 6. μm or less.

A thickness T4 of the insulation layer 105 may be 0.5 μm or more and 40μm or less. The thickness T4 may be 0.5 μm or more and 10 μm or less,from 10 μm or more and 20 μm or less, from 20 μm or more and 30 μm orless, or from 30 μm or more and 40 μm or less.

The insulation layer 105 may include an inorganic insulator or anorganic insulator. The insulation layer 105 may include at least any oneof silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide,aluminum nitride and aluminum oxynitride as an example of the inorganicinsulator.

The insulation layer 105 may include at least any one of a polyimideresin, a polyamide resin, an epoxy resin, a polybenzoxazole resin and aphenol resin as an example of the organic insulator. The organicinsulator may include a photosensitive resin.

The bump structure 106 is formed on the pad portion 113 of the wiringlayer 104. The bump structure 106 includes a UBM (Under Bump Metal)layer 119 and an electroconductive bonding material 120 which arestacked in this order from the side of the wiring layer 104. The UBMlayer 119 is formed inside the pad opening 114 of the insulation layer105.

The UBM layer 119 includes a first electrode layer 121 and a secondelectrode layer 122 which are stacked in this order from the side of thewiring layer 104. The first electrode layer 121 includes at least one ofcopper and nickel. The thickness of the first electrode layer 121 may be0.5 μm or more and 6.0 μm or less. The second electrode layer 122includes at least one of copper and nickel. The thickness of the secondelectrode layer 122 may be 0.5 μm or more and 6.0 μm or less.

The electroconductive bonding material 120 may include a portion whichis positioned inside the pad opening 114 and a portion which ispositioned outside the pad opening 114. The electroconductive bondingmaterial 120 may cover a major surface of the insulation layer 105outside the pad opening 114.

The electroconductive bonding material 120 includes solder or metallicpaste. In the preferred embodiment, the electroconductive bondingmaterial 120 includes solder. The solder may include tin (Sn). Thesolder may include at least anyone of SnAg alloy, SnSb alloy, SnAgCualloy, SnZnBi alloy, SnCu alloy, SnCuNi alloy and SnSbNi alloy. Themetallic paste may include at least any one of aluminum, copper, silverand gold.

The sealing insulation layer 107 seals the base electrode layer 103, thewiring layer 104, the insulation layer 105 and the bump structure 106 onthe major surface 108. The sealing insulation layer 107 enters into thespace 118. Where a chip component is connected to the wiring structurebody 101 through the electroconductive bonding material 120, the sealinginsulation layer 107 also seals the chip component.

The sealing insulation layer 107 may be a photosensitive resin or athermosetting resin. The sealing insulation layer 107 may include atleast anyone of a polyimide resin, a polyamide resin, an epoxy resin, apolybenzoxazole resin and a phenol resin.

FIG. 18A to FIG. 18I are cross-sectional views showing various processsteps in an example of a method for manufacturing the wiring structurebody 101 shown in FIG. 16.

With reference to FIG. 18A, the support substrate 102 is prepared. Thesupport substrate 102 is formed by forming the major surface insulationlayer 110 on a major surface of a semiconductor substrate (siliconsubstrate). The major surface insulation layer 110 may be formed by anoxidation treatment method (for example, a thermal oxidation treatmentmethod) or a CVD (Chemical Vapor Deposition) method.

Then, the base electrode layer 103 is formed on the major surface 108 ofthe support substrate 102. The step of forming the base electrode layer103 includes a step of forming the first electrode layer 111 and thesecond electrode layer 112 in this order from the side of the majorsurface 108. The first electrode layer 111 and the second electrodelayer 112 may be each formed by a sputtering method.

Then, with reference to FIG. 18B, a mask 131 having a predeterminedpattern is formed on the base electrode layer 103. The mask 131 has anopening 132 for exposing a region at which the wiring layer 104 is to beformed in the base electrode layer 103. The mask 131 may be aphotosensitive resin. The opening 132 of the mask 131 is formed by adevelopment step after a photographic exposure step through aphoto-mask.

Then, with reference to FIG. 18C, the wiring layer 104 is formed on thebase electrode layer 103. The wiring layer 104 is formed on a portionwhich is exposed from the opening 132 of the mask 131 in the baseelectrode layer 103. The wiring layer 104 may be formed by anelectrolytic copper plating method. After formation of the wiring layer104, the mask 131 is removed.

Then, with reference to FIG. 18D, the insulation layer 105 is formed onthe base electrode layer 103. The insulation layer 105 covers the wiringlayer 104 entirely. Where the insulation layer 105 includes an inorganicinsulator, the insulation layer 105 may be formed by a CVD method. Wherethe insulation layer 105 includes an organic insulator, the insulationlayer 105 may be formed by coating a photosensitive resin on the majorsurface 108.

Then, with reference to FIG. 18E, an unnecessary portion of theinsulation layer 105 is removed. Where the insulation layer 105 includesan inorganic insulator, the unnecessary portion of the insulation layer105 may be removed by etching through a mask (not shown). Where theinsulation layer 105 includes an organic insulator, the unnecessaryportion of the insulation layer 105 may be removed by the photographicexposure step and the development step. Thereby, the insulation layer105 with a predetermined pattern having a pad opening 114 is formed.

Then, with reference to FIG. 18F, a mask 133 having a predeterminedpattern is formed on the base electrode layer 103 so as to cover theinsulation layer 105. The mask 133 has an opening 134 for exposing thepad opening 114.

Then, the bump structure 106 is formed on the wiring layer 104. In thisstep, the UBM layer 119 is first formed on a portion which is exposedfrom the pad opening 114 in the wiring layer 104. The step of formingthe UBM layer 119 includes a step of forming the first electrode layer121 and the second electrode layer 122 in this order from the side ofthe wiring layer 104.

The first electrode layer 121 may be formed by an electrolytic copperplating method. The second electrode layer 122 may be formed by anelectrolytic nickel plating method. Then, the electroconductive bondingmaterial 120 is formed on the UBM layer 119. The electroconductivebonding material 120 may be formed by an electrolytic solder platingmethod. Thereafter, the mask 133 is removed.

Then, with reference to FIG. 18G, the electroconductive bonding material120 is heated. Thereby, the electroconductive bonding material 120 isshaped into a hemispherical shape. The step of heating theelectroconductive bonding material 120 may be executed at any timingbefore the step of forming the sealing insulation layer 107.

Then, with reference to FIG. 18H, an unnecessary portion of the baseelectrode layer 103 is removed. In this step, an unnecessary portion ofthe second electrode layer 112 is first removed. More specifically, aportion which is exposed from the insulation layer 105 in the secondelectrode layer 112 is removed by etching. The etching may be isotropicetching (for example, wet etching).

In this step, a portion which is positioned directly under a peripheraledge portion of the insulation layer 105 in the second electrode layer112 is also removed. Thereby, a peripheral edge portion of the secondelectrode layer 112 is formed at a region which is further inside thanthe peripheral edge portion of the insulation layer 105.

Then, an unnecessary portion of the first electrode layer 111 isremoved. More specifically, a portion which is exposed from theinsulation layer 105 in the first electrode layer 111 is removed byetching. The etching may be isotropic etching (for example, wetetching).

In this step, a portion which is positioned directly under theperipheral edge portion of the insulation layer 105 in the firstelectrode layer 111 is also removed. Thereby, a peripheral edge portionof the first electrode layer 111 is formed at a region further insidethan the peripheral edge portion of the insulation layer 105. Asdescribed above, there is formed the base electrode layer 103 having apredetermined pattern.

Then, with reference to FIG. 18I, the sealing insulation layer 107 isformed on the major surface 108. The sealing insulation layer 107 fillsthe space 118, thereby sealing the base electrode layer 103, the wiringlayer 104, the insulation layer 105 and the bump structure 106. Thesealing insulation layer 107 may be formed by coating a photosensitiveresin or a thermosetting resin on the major surface 108. The wiringstructure body 101 is formed by the steps including the above.

Where a chip component is connected to the bump structure 106(electroconductive bonding material 120), the chip component isconnected to the bump structure 106 (electroconductive bonding material120), prior to the step of forming the sealing insulation layer 107.

As described so far, according to the wiring structure body 101, theinsulation layer 105 is formed on a peripheral edge portion of the baseelectrode layer 103 so as to protrude to a region outside the baseelectrode layer 103 from above the base electrode layer 103. Further,the electroconductive bonding material 120 is formed on the wiring layer104. Thereby, it is possible to prevent the molten electroconductivebonding material 120 from wetting and spreading by the insulation layer105 and, thus, possible to prevent the electroconductive bondingmaterial 120 from outflowing.

More specifically, the insulation layer 105 covers the wiring layer 104and has the pad opening 114 which exposes the pad portion 113 of thewiring layer 104. Inside the pad opening 114, there is formed the bumpstructure 106 which includes the electroconductive bonding material 120.Thereby, it is possible to prevent the electroconductive bondingmaterial 120 from making contact with the wiring layer 104 and, thus,possible to appropriately prevent the molten electroconductive bondingmaterial 120 from outflowing by the insulation layer 105.

The base electrode layer 103 is also positioned at a region furtherinside than the insulation layer 105. Therefore, even if the moltenelectroconductive bonding material 120 oozes outside the wiring layer104, the electroconductive bonding material 120 can spread to the baseelectrode layer 103 at a region further inside than the insulation layer105. Thereby, it is possible to appropriately prevent theelectroconductive bonding material 120 from outflowing to a regionoutside the insulation layer 105.

Further, according to the wiring structure body 101, the space 118defined at a region between the protruding portion 117 of the insulationlayer 105 and the major surface 108 of the support substrate 102 issealed by the sealing insulation layer 107. Thereby, where the moltenelectroconductive bonding material 120 is present at the space 118, theelectroconductive bonding material 120 can be sealed inside the space118 by the sealing insulation layer 107. Thus, it is possible toappropriately prevent the electroconductive bonding material 120 fromoutflowing.

FIG. 19 is a plan view which shows a wiring structure body 141 accordingto the sixth preferred embodiment of the present invention. FIG. 20 is across-sectional view which is taken along line XX-XX shown in FIG. 19.In the following, structures corresponding to the structures in thewiring structure body 101 (refer to FIG. 16, FIG. 17 and others) will begiven the same reference signs, and a description thereof is omitted.

With reference to FIG. 19 and FIG. 20, the wiring structure body 141includes a support substrate 102, a base electrode layer 103, a wiringlayer 104, an insulation layer 105, a bump structure 106 and a sealinginsulation layer 107. In FIG. 19 and FIG. 20, there is shown a statethat a chip component is not connected to the wiring structure body 141.In FIG. 19, an internal structure of the wiring structure body 141 isshown by seeing through the sealing insulation layer 107.

A second electrode layer 112 of the base electrode layer 103 protrudesto a region outside a first electrode layer 111 from above the firstelectrode layer 111. The second electrode layer 112 protrudes in atransverse direction along a major surface of the first electrode layer111. The second electrode layer 112 faces a major surface 108 in anormal direction of the major surface 108 at the region outside thefirst electrode layer 111.

More specifically, the second electrode layer 112 includes an electrodebase portion 142 and an electrode protruding portion 143. The electrodebase portion 142 covers the first electrode layer 111. The electrodeprotruding portion 143 extends from the electrode base portion 142 to aside opposite to the first electrode layer 111.

More specifically, the electrode protruding portion 143 extends in thetransverse direction along the major surface of the first electrodelayer 111 and protrudes to the region outside the first electrode layer111. The electrode protruding portion 143 faces the major surface 108 ina normal direction of the major surface 108 at the region outside thefirst electrode layer 111. The electrode protruding portion 143 definesa first space 144 together with the major surface 108 and a side surfaceof the first electrode layer 111. The first space 144 is recessed towardthe side of the first electrode layer 111.

A ratio W2/T1, which is a ratio of a width W2 of the electrodeprotruding portion 143 in relation to the thickness T1 of the firstelectrode layer in, may be 1 or more and 10 or less. The ratio W2/T1 maybe 1 or more and 2 or less, from 2 or more and 4 or less, from 4 or moreand 6 or less, from 6 or more and 8 or less, or from 8 or more and 10 orless. It is preferable that the ratio W2/T1 is 1 or more and 5 or less.

The width W2 may be 0.01 μm or more and 6.0 μm or less. The width W2 maybe 0.01 μm or more and 1.0 μm or less, from 1.0 μm or more and 2.0 μm orless, from 2.0 μm or more and 3.0 μm or less, from 3.0 μm or more and4.0 μm or less, from 4.0 μm or more and 5.0 μm or less, or from 5.0 μmor more and 6.0 μm or less.

The wiring layer 104 is formed on the base electrode layer 103. Thewiring layer 104 covers collectively the electrode base portion 142 andthe electrode protruding portion 143 of the second electrode layer 112.More specifically, the wiring layer 104 includes a wiring base portion145 and a wiring protruding portion 146.

The wiring base portion 145 covers the electrode base portion 142 of thesecond electrode layer 112. The wiring protruding portion 146 covers theelectrode protruding portion 143 of the second electrode layer 112. Inthe preferred embodiment, a side surface of the wiring layer 104 isconnected to a side surface of the second electrode layer 112 withoutany difference in level.

The wiring protruding portion 146 may protrude to a region outside thesecond electrode layer 112 from above the second electrode layer 112.The wiring protruding portion 146 may face the major surface 108 in anormal direction of the major surface 108 at the region outside thesecond electrode layer 112. More specifically, the wiring protrudingportion 146 may protrude in a transverse direction along a major surfaceof the second electrode layer 112. A step portion may be formed betweenthe side surface of the wiring layer 104 and the side surface of thesecond electrode layer 112.

The insulation layer 105 is formed on the wiring layer 104. Theinsulation layer 105 protrudes to a region outside the wiring layer 104from above the wiring layer 104. The insulation layer 105 protrudes in atransverse direction along a major surface of the wiring layer 104. Theinsulation layer 105 faces the major surface 108 in a normal directionof the major surface 108 at the region outside the wiring layer 104. Theinsulation layer 105 exposes the side surface of the wiring layer 104.

More specifically, the insulation layer 105 includes an insulating baseportion 147 and an insulating protruding portion 148. The insulatingbase portion 147 covers the wiring base portion 145 of the wiring layer104. The insulating protruding portion 148 covers the wiring protrudingportion 146 of the wiring layer 104. The insulating protruding portion148 extends in the transverse direction along the major surface of thewiring layer 104 and protrudes to the region outside the wiring layer104. The width of the insulating protruding portion 148 may be equal toor more than the thickness T1 of the first electrode layer 111.

The insulating protruding portion 148 faces the major surface 108 in thenormal direction of the major surface 108 at the region outside thewiring layer 104. The insulating protruding portion 148 defines a secondspace 149 together with the major surface 108 and the side surface ofthe wiring layer 104. The second space 149 is recessed toward the sideof the wiring layer 104. The second space 149 is communicativelyconnected to the first space 144.

A thickness T5 of the insulation layer 105 may be 0.5 μm or more and 40μm or less. The thickness T5 may be 0.5 μm or more and 10 μm or less,from 10 μm or more and 20 μm or less, from 20 μm or more and 30 μm orless, or from 30 μm or more and 40 μm or less.

The bump structure 106 is formed inside a pad opening 114 of theinsulation layer 105. The pad opening 114 exposes the wiring baseportion 145 of the wiring layer 104. Therefore, the bump structure 106is connected to the wiring base portion 145 of the wiring layer 104.

The sealing insulation layer 107 seals the base electrode layer 103, thewiring layer 104, the insulation layer 105 and the bump structure 106 onthe major surface 108. The sealing insulation layer 107 fills the firstspace 144 and the second space 149. Where a chip component is connectedto the wiring structure body 141 through an electroconductive bondingmaterial 120, the sealing insulation layer 107 also seals the chipcomponent.

FIG. 21A to FIG. 21F are cross-sectional views showing various processsteps in an example of a method for manufacturing the wiring structurebody 141 shown in FIG. 19.

With reference to FIG. 21A, by substantially the same steps as thosedescribed previously in FIG. 18A to FIG. 18D, the base electrode layer103, the wiring layer 104 and the insulation layer 105 are formed on thesupport substrate 102.

Then, with reference to FIG. 21B, an unnecessary portion of theinsulation layer 105 is removed. In the preferred embodiment, a regionat which the pad opening 114 is to be formed in the insulation layer 105and a region outside the wiring layer 104 are removed. Thereby, theinsulation layer 105 is formed only on the wiring layer 104.

Then, with reference to FIG. 21C, by substantially the same steps asthose in FIG. 18F to FIG. 18G, the bump structure 106 is formed.

Then, with reference to FIG. 21D, an unnecessary portion of the baseelectrode layer 103 is removed. In this step, an unnecessary portion ofthe second electrode layer 112 is first removed. More specifically, aportion which is exposed from the wiring layer 104 in the secondelectrode layer 112 is removed by etching. The etching may be isotropicetching (for example, wet etching).

In this step, a portion which is exposed from the insulation layer 105in the wiring layer 104 is also removed. The wiring layer 104 is removedonly by a portion which corresponds to the thickness T2 of the secondelectrode layer 112. Thereby, the side surface of the wiring layer 104and the side surface of the second electrode layer 112 are formed at aregion further inside than a peripheral edge portion of the insulationlayer 105.

Then, with reference to FIG. 21E, an unnecessary portion of the firstelectrode layer 111 is removed. More specifically, a portion which isexposed from the second electrode layer 112 in the first electrode layer111 is removed by etching. The etching may be isotropic etching (forexample, wet etching).

In this step, a portion which is positioned directly under a peripheraledge portion of the second electrode layer 112 in the first electrodelayer 111 is also removed. Thereby, a peripheral edge portion of thefirst electrode layer 111 is formed at a region which is further insidethan the peripheral edge portion of the second electrode layer 112. Asdescribed above, there is formed the base electrode layer 103 having apredetermined pattern.

Then, with reference to FIG. 21F, the sealing insulation layer 107 isformed on the major surface 108. The sealing insulation layer 107 fillsthe first space 144 and the second space 149, thereby sealing the baseelectrode layer 103, the wiring layer 104, the insulation layer 105 andthe bump structure 106. The wiring structure body 141 is formed by thesteps including the above.

Where a chip component is connected to the bump structure 106(electroconductive bonding material 120), the chip component isconnected to the bump structure 106 (electroconductive bonding material120) prior to the step of forming the sealing insulation layer 107.

As described so far, the wiring structure body 141 includes the wiringlayer 104 which is formed on the base electrode layer 103 so as toprotrude to a region outside the base electrode layer 103. Theinsulation layer 105 is formed on the wiring layer 104 so as to expose apad portion 113 of the wiring layer 104. The electroconductive bondingmaterial 120 is formed on the pad portion 113. Thereby, the moltenelectroconductive bonding material 120 can be prevented from wetting andspreading by the insulation layer 105. Thus, it is possible to preventthe electroconductive bonding material 120 from outflowing.

More specifically, the insulation layer 105 has the pad opening 114which exposes the pad portion 113 of the wiring layer 104. The bumpstructure 106 which includes the electroconductive bonding material 120is formed inside the pad opening 114. Thereby, it is possible to preventthe electroconductive bonding material 120 from making contact with thewiring layer 104 and then possible to appropriately prevent the moltenelectroconductive bonding material 120 from outflowing by the insulationlayer 105.

The base electrode layer 103 is positioned at a region further insidethan the wiring layer 104. Therefore, even if the moltenelectroconductive bonding material 120 oozes outside the insulationlayer 105, the molten electroconductive bonding material 120 can spreadto the wiring layer 104 and the base electrode layer 103. Theelectroconductive bonding material 120 spreads along the base electrodelayer 103 at the region further inside than the wiring layer 104.Thereby, it is possible to appropriately prevent the electroconductivebonding material 120 from outflowing to a region outside the wiringlayer 104.

Further, the first space 144 which is defined at a region between themajor surface 108 and the protruding portion 117 of the wiring layer 104is filled with the sealing insulation layer 107. Thereby, where themolten electroconductive bonding material 120 is present at the firstspace 144, the electroconductive bonding material 120 can be sealedinside the first space 144. It is, thus, possible to appropriatelyprevent the molten electroconductive bonding material 120 fromoutflowing.

Further, the second space 149 defined at a region between the majorsurface 108 and the insulating protruding portion 148 of the insulationlayer 105 is filled with the sealing insulation layer 107. Thereby,where the molten electroconductive bonding material 120 is present atthe second space 149, the electroconductive bonding material 120 can besealed inside the second space 149. It is, thus, possible toappropriately prevent the molten electroconductive bonding material 120from outflowing.

FIG. 22 is a cross-sectional view which shows a wiring structure body151 according to the seventh preferred embodiment of the presentinvention. In the following, structures corresponding to the structuresin the wiring structure body 141 (refer to FIG. 19, FIG. 20 and others)will be given the same reference signs, and a description thereof isomitted.

With reference to FIG. 22, in the preferred embodiment, an insulationlayer 105 is free of an insulating protruding portion 148. Theinsulation layer 105 is formed at a region further inside than aperipheral edge portion of a wiring layer 104. The insulation layer 105covers at least a wiring base portion 145 of the wiring layer 104. Theinsulation layer 105 may cover portion a wiring protruding portion 146of the wiring layer 104.

There is formed a recess portion 152 which is recessed toward the sideof a base electrode layer 103 at an exposed portion which is exposedfrom the insulation layer 105 on a major surface of the wiring layer104. The recess portion 152 may be connected to a side surface of theinsulation layer 105 without any difference in level.

The wiring structure body 151 is manufactured by forming the insulationlayer 105 at a region which is further inside than the peripheral edgeportion of the wiring layer 104 in the previously described step offorming the insulation layer 105 (refer to FIG. 21B). The recess portion152 is formed by removing a portion of the wiring layer 104 in thepreviously described step of removing the second electrode layer 112(refer to FIG. 21D).

As described so far, the wiring structure body 151 is also able toprovide substantially the same technical effects as those described withregard to the wiring structure body 141.

FIG. 23 is a plan view which shows a wiring structure body 161 accordingto the eighth preferred embodiment of the present invention. FIG. 24 isa cross-sectional view which is taken along line XXIV-XXIV shown in FIG.23. In the following, structures corresponding to the structures in thewiring structure body 101 (refer to FIG. 16, FIG. 17 and others) will begiven the same reference signs, and a description thereof is omitted.

With reference to FIG. 23 and FIG. 24, the wiring structure body 161includes a base electrode layer 103, a wiring layer 104, an insulationlayer 105, a bump structure 106, a sealing insulation layer 107, a baseinsulation layer 162 and a terminal electrode layer 163. In FIG. 23 andFIG. 24, there is shown a state that a chip component is not connectedto the wiring structure body 161. In FIG. 23, there is shown an internalstructure of the wiring structure body 161 by seeing through the sealinginsulation layer 107.

The wiring structure body 161 is different from the previously describedwiring structure body 101 in that it does not include a supportsubstrate 102. A protruding portion 117 of the insulation layer 105forms a step portion 165 between itself and the base electrode layer 103in place of a space 118.

The sealing insulation layer 107 seals the wiring layer 104, theinsulation layer 105 and the bump structure 106. The sealing insulationlayer 107 covers the step portion 165 so as to expose the base electrodelayer 103. A portion which covers the step portion 165 in the sealinginsulation layer 107 forms a stopper portion which prevents theinsulation layer 105 from falling off from the sealing insulation layer107. Where a chip component is connected to the wiring structure body161 through the electroconductive bonding material 120, the sealinginsulation layer 107 also seals the chip component.

The sealing insulation layer 107 exposes a major surface of the baseelectrode layer 103 at a side thereof opposite to the wiring layer 104.In the following, the exposed surface of the base electrode layer 103 isreferred to as an electrode surface 164. The electrode surface 164 ofthe base electrode layer 103 is formed by a first electrode layer 111.The electrode surface 164 of the base electrode layer 103 is formed soas to be flush with an outer surface of the sealing insulation layer107. One flat surface is formed by the electrode surface 164 of the baseelectrode layer 103 and an outer surface of the sealing insulation layer107. This flat surface is not a ground surface.

The base insulation layer 162 covers the electrode surface 164 of thebase electrode layer 103. A major surface of the base insulation layer162 on a side thereof opposite to the base electrode layer 103 is anexposed surface which is exposed outside. The base insulation layer 162extends from the side of the base electrode layer 103 to the side of thesealing insulation layer 107 to cover an outer surface of the sealinginsulation layer 107.

More specifically, the base insulation layer 162 collectively covers aflat surface formed by the base electrode layer 103 and the sealinginsulation layer 107. The base insulation layer 162 faces the protrudingportion 117 of the insulation layer 105 with the sealing insulationlayer 107 (stopper portion) interposed therebetween. Thereby, it ispossible to appropriately prevent the insulation layer 105 from fallingoff.

The base insulation layer 162 may include an inorganic insulator or anorganic insulator. The base insulation layer 162 may include at leastany one of silicon oxide, silicon nitride, silicon oxynitride, aluminumoxide, aluminum nitride and aluminum oxynitride as an example of theinorganic insulator.

The base insulation layer 162 may include at least anyone of a polyimideresin, a polyamide resin, an epoxy resin, a polybenzoxazole resin and aphenol resin as an example of the organic insulator. The organicinsulator may include a photosensitive resin.

The base insulation layer 162 includes a lower pad opening 166 whichexposes any given region of the electrode surface 164 of the baseelectrode layer 103 as a pad portion. In the preferred embodiment, thelower pad opening 166 is formed at a region which will not overlap withthe bump structure 106 in plan view.

The terminal electrode layer 163 penetrates through the base insulationlayer 162 and is connected to the base electrode layer 103. Morespecifically, the terminal electrode layer 163 is formed inside thelower pad opening 166 of the base insulation layer 162. That is, theterminal electrode layer 163 is formed at a region which will notoverlap with bump structure 106 in plan view. The terminal electrodelayer 163 is connected to the base electrode layer 103 inside the lowerpad opening 166.

The terminal electrode layer 163 protrudes from a major surface of thebase insulation layer 162 in a direction opposite to the base electrodelayer 103. The terminal electrode layer 163 may be formed as an externalterminal electrode which is to be connected externally. The terminalelectrode layer 163 may have an overlap portion which covers the majorsurface of the base insulation layer 162. The terminal electrode layer163 may have a stacked-layer structure which includes an Ni layer, a Pdlayer and an Au layer formed in this order from the side of the baseelectrode layer 103.

FIG. 25A to FIG. 25E are cross-sectional views showing various processsteps in an example of a method for manufacturing the wiring structurebody 161 shown in FIG. 23.

With reference to FIG. 25A, a support substrate 171 is prepared. Anymember may be used in the support substrate 171 as long as the membercan be removed in the middle of the manufacturing. The support substrate171 is removed by grinding, detachment and/or etching of the supportsubstrate 171.

The support substrate 171 may be a semiconductor substrate or a metalsubstrate. The semiconductor substrate may be a silicon substrate. Themetal substrate may be a copper substrate or a stainless steelsubstrate. In the following, a description will be given of a case wherethe support substrate 171 is made up of a stainless steel substrate.

After the support substrate 171 has been prepared, a resin layer 172 isformed on a major surface of the support substrate 171. The resin layer172 is also called a permanent film. The resin layer 172 may include anegative type photosensitive resin.

The resin layer 172 may be formed by sticking a film-shaped resin sheetto the major surface of the support substrate 171. The resin layer 172may be formed by coating a liquid resin on the major surface of thesupport substrate 171. The resin layer 172 is cured by a photographicexposure step.

Then, with reference to FIG. 25B, a sealing structure 173 which includesthe base electrode layer 103, the wiring layer 104, the insulation layer105, the bump structure 106 and the sealing insulation layer 107 isformed on the resin layer 172. The sealing structure 173 is formed bysubstantially the same steps as those of the method for manufacturingthe wiring structure body 101 (refer to FIG. 18A to FIG. 18I).

The sealing structure 173 is formed on a major surface of the resinlayer 172. Therefore, a surface of the sealing structure 173 which makescontact with the resin layer 172 (hereinafter, referred to as “lowersurface”) is formed to be flat. The lower surface of the sealingstructure 173 is formed by the electrode surface 164 of the baseelectrode layer 103 and the sealing insulation layer 107. The lowersurface of the sealing structure 173 is not a ground surface.

Then, with reference to FIG. 25C, the sealing structure 173 is detachedfrom the resin layer 172. Thereby, the lower surface of the sealingstructure 173 is exposed. On the lower surface of the sealing structure173, the electrode surface 164 of the base electrode layer 103 is formedso as to be flush with an outer surface of the sealing insulation layer107. The support substrate 171 detached from the sealing structure 173may be reused as a support substrate for manufacturing another wiringstructure body 161.

Then, with reference to FIG. 25D, the base insulation layer 162 isformed on the lower surface of the sealing structure 173. Morespecifically, the base insulation layer 162 covers the base electrodelayer 103 and the sealing insulation layer 107. Where the baseinsulation layer 162 includes an inorganic insulator, the baseinsulation layer 162 may be formed by a CVD method. Where the baseinsulation layer 162 includes an organic insulator, the base insulationlayer 162 may be formed by coating a photosensitive resin on the lowersurface of the sealing structure 173.

Then, with reference to FIG. 25E, a pad opening 114 which exposes thebase electrode layer 103 is formed in the base insulation layer 162.Where the base insulation layer 162 includes an inorganic insulator, anunnecessary portion of the base insulation layer 162 may be removed byetching through a mask (not shown). Where the base insulation layer 162includes an organic insulator, the unnecessary portion of the baseinsulation layer 162 may be removed by a photographic exposure step anda development step. Thereby, the base insulation layer 162 whichincludes the pad opening 114 is formed.

Then, the terminal electrode layer 163 is formed inside the lower padopening 166. The step of forming the terminal electrode layer 163includes a step of forming an Ni layer, a Pd layer and an Au layer inthis order from the side of the base electrode layer 103. The Ni layer,the Pd layer and the Au layer may be individually formed by anelectroless plating method. The wiring structure body 161 ismanufactured by the steps including the above.

Where a chip component is connected to the bump structure 106(electroconductive bonding material 120), the chip component isconnected to the bump structure 106 (electroconductive bonding material120) prior to the step of forming the sealing insulation layer 107.

As described so far, the wiring structure body 161 is also able toprovide substantially the same technical effects as those described inthe wiring structure body 101.

FIG. 26 is a plan view which shows a wiring structure body 181 accordingto the ninth preferred embodiment of the present invention. FIG. 27 is across-sectional view which is taken along line XXVII-XXVII shown in FIG.26. In the following, structures corresponding to the structures in thewiring structure body 161 (refer to FIG. 23, FIG. 24 and others) will begiven the same reference signs, and a description thereof is omitted.

With reference to FIG. 26 and FIG. 27, the wiring structure body 181includes abase electrode layer 103, a wiring layer 104, an insulationlayer 105, a bump structure 106, a sealing insulation layer 107, a baseinsulation layer 162 and a terminal electrode layer 163. In FIG. 26 andFIG. 27, there is shown a state that a chip component is not connectedto the wiring structure body 181. In FIG. 26, there is shown an internalstructure of the wiring structure body 181 by seeing through the sealinginsulation layer 107.

A second electrode layer 112 of the base electrode layer 103 protrudesto a region outside the base electrode layer 103 from above a firstelectrode layer 111. The second electrode layer 112 protrudes in atransverse direction along a major surface of the first electrode layer111. More specifically, the second electrode layer 112 includes anelectrode base portion 182 and an electrode protruding portion 183.

The electrode base portion 182 covers the first electrode layer 111. Theelectrode protruding portion 183 extends from the electrode base portion182 to aside opposite to the first electrode layer 111. Morespecifically, the electrode protruding portion 183 extends in thetransverse direction along the major surface of the first electrodelayer 111 and protrudes to a region outside the first electrode layer111. The electrode protruding portion 183 forms a first step portion 184between itself and a side surface of the first electrode layer 111.

A ratio W3/T1, which is a ratio of a width W3 of the electrodeprotruding portion 183 in relation to the thickness T1 of the firstelectrode layer 111, may be 1 or more and 10 or less. The ratio W3/T1may be 1 or more and 2 or less, from 2 or more and 4 or less, from 4 ormore and 6 or less, from 6 or more and 8 or less, or from 8 or more and10 or less. It is preferable that the ratio W3/T1 is 1 or more and 5 orless.

The width W3 of the electrode protruding portion 183 may be 0.01 μm ormore and 5.0 μm or less. The width W3 may be 0.01 μm or more and 1.0 μmor less, from 1.0 μm or more and 2.0 μm or less, from 2.0 μm or more and3.0 μm or less, from 3.0 μm or more and 4.0 μm or less, or from 4.0 μmor more and 5.0 μm or less.

The wiring layer 104 is formed on the base electrode layer 103. Thewiring layer 104 covers collectively the electrode base portion 182 andthe electrode protruding portion 183 of the second electrode layer 112.More specifically, the wiring layer 104 includes a wiring base portion185 and a wiring protruding portion 186.

The wiring base portion 185 covers the electrode base portion 182 of thesecond electrode layer 112. The wiring protruding portion 186 covers theelectrode protruding portion 183 of the second electrode layer 112. Aside surface of the wiring layer 104 may be connected to a side surfaceof the second electrode layer 112 without any difference in level.

The wiring protruding portion 186 may protrude to a region outside thesecond electrode layer 112 from above the second electrode layer 112.The wiring protruding portion 186 may protrude in a transverse directionalong a major surface of the second electrode layer 112. A step portionmay be formed between the side surface of the wiring layer 104 and theside surface of the second electrode layer 112.

The insulation layer 105 is formed on the wiring layer 104. Theinsulation layer 105 protrudes to a region outside the wiring layer 104from above the wiring layer 104. The insulation layer 105 protrudes in atransverse direction along a major surface of the wiring layer 104. Theinsulation layer 105 exposes the side surface of the wiring layer 104.More specifically, the insulation layer 105 includes an insulating baseportion 187 and an insulating protruding portion 188.

The insulating base portion 187 covers the wiring base portion 185 ofthe wiring layer 104. The insulating protruding portion 188 covers thewiring protruding portion 186 of the wiring layer 104. The insulatingprotruding portion 188 extends in the transverse direction along themajor surface of the wiring layer 104 and protrudes to the regionoutside the wiring layer 104. The insulating protruding portion 188forms a second step portion 189 between itself and the side surface ofthe wiring layer 104. The width of the insulating protruding portion 188may be equal to or more than the thickness T1 of the first electrodelayer 111.

A thickness T6 of the insulation layer 105 may be 0.5 μm or more and 40μm or less. The thickness T6 may be 0.5 μm or more and 10 μm or less,from 10 μm or more and 20 μm or less, from 20 μm or more and 30 μm orless, or from 30 μm or more and 40 μm or less.

The sealing insulation layer 107 seals the wiring layer 104, theinsulation layer 105 and the bump structure 106. The sealing insulationlayer 107 covers the first step portion 184 and the second step portion189 and exposes an electrode surface 164 of the base electrode layer103. Where a chip component is connected to the wiring structure body181 through the electroconductive bonding material 120, the sealinginsulation layer 107 also seals the chip component.

A portion which covers the first step portion 184 in the sealinginsulation layer 107 forms a first stopper portion which prevents thewiring layer 104 from falling off from the sealing insulation layer 107.A portion which covers the second step portion 189 in the sealinginsulation layer 107 forms a second stopper portion which prevents theinsulation layer 105 from falling off from the sealing insulation layer107.

The base insulation layer 162 faces the electrode protruding portion 183of the wiring layer 104 and the insulating protruding portion 188 of theinsulation layer 105 with the sealing insulation layer 107 (the firststopper portion and the second stopper portion) interposed therebetween.Thereby, the wiring layer 104 and the insulation layer 105 areappropriately prevented from falling off.

FIG. 28A to FIG. 28F are cross-sectional views showing various processsteps in an example of a method for manufacturing the wiring structurebody 181 shown in FIG. 26.

With reference to FIG. 28A, a resin layer 172 is formed on a supportsubstrate 171 by substantially the same step as the step describedpreviously in FIG. 25A. Then, the base electrode layer 103, the wiringlayer 104 and the insulation layer 105 are formed on the resin layer 172by substantially the same steps as those described previously in FIG.18B to FIG. 18D.

Then, with reference to FIG. 28B, an unnecessary portion of theinsulation layer 105 is removed. In the preferred embodiment, a regionat which a pad opening 114 is to be formed in the insulation layer 105and a region outside the wiring layer 104 are removed. Thereby, theinsulation layer 105 is formed only on the wiring layer 104.

Then, with reference to FIG. 28C, the bump structure 106 is formed bysubstantially the same steps as those described previously in FIG. 18Fto FIG. 18G.

Then, with reference to FIG. 28D, an unnecessary portion of the baseelectrode layer 103 is removed. In this step, an unnecessary portion ofthe second electrode layer 112 is first removed. More specifically, aportion which is exposed from the wiring layer 104 in the secondelectrode layer 112 is removed by etching. The etching may be isotropicetching (for example, wet etching).

In this step, a portion which is exposed from the insulation layer 105in the wiring layer 104 is also removed. The wiring layer 104 is removedonly by a portion corresponding to the thickness T2 of the secondelectrode layer 112. Thereby, a side surface of the wiring layer 104 anda side surface of the second electrode layer 112 are formed at a regionfurther inside than a peripheral edge portion of the insulation layer105.

Then, with reference to FIG. 28E, an unnecessary portion of the firstelectrode layer 111 is removed. More specifically, a portion which isexposed from the second electrode layer 112 in the first electrode layer111 is removed by etching. The etching may be isotropic etching (forexample, wet etching).

In this step, a portion which is positioned directly under a peripheraledge portion of the second electrode layer 112 in the first electrodelayer 111 is also removed by etching. Thereby, a peripheral edge portionof the first electrode layer 111 is formed at a region further insidethan the peripheral edge portion of the second electrode layer 112. Asdescribed above, there is formed the base electrode layer 103 having apredetermined pattern.

Then, with reference to FIG. 28F, the sealing insulation layer 107 isformed on the resin layer 172. Thereby, a sealing structure 173 isformed. Thereafter, the wiring structure body 181 is manufactured bysubstantially the same step as those described previously in FIG. 25C toFIG. 25E.

Where a chip component is connected to the bump structure 106(electroconductive bonding material 120), the chip component isconnected to the bump structure 106 (electroconductive bonding material120) prior to the step of forming the sealing insulation layer 107.

As described so far, the wiring structure body 181 is also able toprovide substantially the same technical effects as those described inthe wiring structure body 161.

FIG. 29 is a cross-sectional view which shows a wiring structure body191 according to the tenth preferred embodiment of the presentinvention. In the following, structures corresponding to the structuresin the wiring structure body 181 (refer to FIG. 26, FIG. 27 and others)will be given the same reference signs, and a description thereof isomitted.

With reference to FIG. 29, the wiring structure body 191 is differentfrom the wiring structure body 181 in that an insulation layer 105 isfree of an insulating protruding portion 188. The insulation layer 105is formed at a region further inside than a peripheral edge portion of awiring layer 104. The insulation layer 105 covers at least a wiring baseportion 185 of the wiring layer 104. The insulation layer 105 may covera portion of a wiring protruding portion 186 of the wiring layer 104.

At an exposed portion which is exposed from the insulation layer 105 ina major surface of the wiring layer 104, there is formed a recessportion 192 which is recessed toward the side of a base electrode layer103. The recess portion 192 may be connected to a side surface of theinsulation layer 105 without any difference in level.

The wiring structure body 191 is manufactured by forming the insulationlayer 105 at a region further inside than a peripheral edge portion ofthe wiring layer 104 in the previously described step of forming theinsulation layer 105 (refer to FIG. 28B). The recess portion 192 isformed by removing a portion of the wiring layer 104 in the previouslydescribed step of removing the second electrode layer 112 (refer to FIG.28D).

As described so far, the wiring structure body 191 is also able toprovide substantially the same technical effects as those described inthe wiring structure body 181.

FIG. 30 is a plan view which shows an electronic component 201 accordingto the eleventh preferred embodiment of the present invention. FIG. 31is a cross-sectional view which is taken along line XXXI-XXXI shown inFIG. 30. The electronic component 201 is an electronic component inwhich the previously described wiring structure body 101 (refer to FIG.16 and FIG. 17) is incorporated. In the following, structurescorresponding to the structures in the wiring structure body 101 will begiven the same reference signs, and some of descriptions including thoseon dimensions, etc., of each structure of the wiring structure body 101will be omitted.

The electronic component 201 includes an interposer 202 as a pitchconversion substrate, a plurality of wiring structure bodies 101, a chipcomponent 203, a plurality of electrode bodies 204, a sealing insulationlayer 205 and a plurality of external terminals 206.

The interposer 202 and the sealing insulation layer 205 correspond tothe support substrate 102 and the sealing insulation layer 107 of thewiring structure body 101. That is, in the preferred embodiment, thewiring structure bodies 101 each include a portion of the interposer202, a portion of the sealing insulation layer 205, the base electrodelayer 103, the wiring layer 104, the insulation layer 105 and the bumpstructure 106.

The interposer 202 has a first major surface 207 on one side, a secondmajor surface 208 on the other side and a side surface 209 whichconnects the first major surface 207 and the second major surface 208.The first major surface 207 and the second major surface 208 are bothformed so as to be flat. The first major surface 207 and the secondmajor surface 208 are formed in a quadrangle shape (in a rectangularshape in the preferred embodiment) in a plan view taken from theirnormal directions (hereinafter, simply referred to as “plan view”).

The interposer 202 includes a base body 210 and a major surfaceinsulation layer 211. The base body 210 and the major surface insulationlayer 211 correspond respectively to the base body 109 and the majorsurface insulation layer 110 of the wiring structure body 101. The basebody 210 may be a semiconductor substrate. The base body 210 may be asilicon substrate. The major surface insulation layer 211 covers a majorsurface of the base body 210. The major surface insulation layer 211 mayinclude silicon oxide or silicon nitride.

A chip region 212 and an outer region 213 are set in the interposer 202.The chip region 212 is a region at which the chip component 203 isdisposed. The chip region 212 is set at a center portion of the majorsurface insulation layer 211. The chip region 212 is set in a quadrangleshape corresponding to a planar shape of the chip component 203 in planview. The outer region 213 is a region outside the chip region 212. Theouter region 213 is set in an endless shape (quadrangular annular shape)which surrounds the chip region 212 in plan view.

The plurality of wiring structure bodies 101 (four in the preferredembodiment) are formed to be spaced from each other on the first majorsurface 207 of the interposer 202. The plurality of wiring structurebodies 101 each extend over the chip region 212 and the outer region213. The plurality of wiring structure body 101 each include a first padregion 221, a second pad region 222 and a wiring region 223.

The first pad region 221 of each of the wiring structure bodies 101 isformed at the chip region 212. A chip component 203 which will bedescribed later is connected to each of the first pad region 221. In thepreferred embodiment, the first pad regions 221 are each formed in aquadrangle shape in plan view. The first pad regions 221 are not limitedto be each formed in a quadrangle shape but may be each formed in anygiven planar shape.

The second pad region 222 of each of the wiring structure bodies 101 isformed at the outer region 213. An electrode body 204 which will bedescribed later is connected to each of the second pad regions 222. Inthe preferred embodiment, the second pad regions 222 are each formed ina quadrangle shape in plan view. The second pad regions 222 are notlimited to be each formed in a quadrangle shape but may be each formedin any given planar shape.

The wiring region 223 of each of the wiring structure bodies 101connects the first pad region 221 and the second pad region 222 of thecorresponding wiring layer 104. The wiring regions 223 are each drawnaround in a line shape at a region between the first pad region 221 andthe second pad region 222 of the corresponding wiring layer 104. Thewiring regions 223 may be each drawn around in any mode.

The base electrode layer 103 of each of the wiring structure bodies 101is formed on the first major surface 207 of the interposer 202. The baseelectrode layer 103 has a planar shape corresponding to the first padregion 221, the second pad region 222 and the wiring region 223.

The base electrode layer 103 has a stacked-layer structure whichincludes a first electrode layer 111 and a second electrode layer 112stacked in this order from the side of the interposer 202. A sidesurface of the second electrode layer 112 may be formed so as to beflush with a side surface of the first electrode layer 111. The sidesurface of the second electrode layer 112 may protrude outside inrelation to the side surface of the first electrode layer 111. The sidesurface of the second electrode layer 112 may be formed inside inrelation to the side surface of the first electrode layer 111.

The wiring layer 104 of each of the wiring structure bodies 101 isformed on the base electrode layer 103. The wiring layer 104 has aplanar shape corresponding to the first pad region 221, the second padregion 222 and the wiring region 223. The wiring layer 104 is formed tobe spaced inwardly from a peripheral edge portion of the base electrodelayer 103, and exposes the peripheral edge portion of the base electrodelayer 103.

The wiring layer 104 includes a first pad portion 224 (connectionportion) and a second pad portion 225. The first pad portion 224corresponds to the previously described pad portion 113 (refer to FIG.16, FIG. 17 and others). The first pad portion 224 is formed at thefirst pad region 221. The second pad portion 225 is formed at the secondpad region 222.

The insulation layer 105 of each of the wiring structure bodies 101 isformed on the base electrode layer 103. The insulation layer 105 has aplanar shape corresponding to the first pad region 221, the second padregion 222 and the wiring region 223. A first pad opening 226 covers thewiring layer 104 so as to expose the first pad portion 224 and thesecond pad portion 225 of the wiring layer 104. Thereby, the first padopening 226 and a second pad opening 227 are formed in the insulationlayer 105.

The insulation layer 105 protrudes to a region outside the baseelectrode layer 103 from above a peripheral edge portion of the baseelectrode layer 103. The insulation layer 105 protrudes in a transversedirection along a major surface of the base electrode layer 103. Theinsulation layer 105 faces the first major surface 207 in a normaldirection of the first major surface 207 at the region outside the baseelectrode layer 103.

More specifically, the insulation layer 105 includes a base portion 115,a covering portion 116 and a protruding portion 117. The base portion115 is formed on the peripheral edge portion of the base electrode layer103. The covering portion 116 extends from the base portion 115 towardabove the wiring layer 104 and demarcate the first pad opening 226 andthe second pad opening 227.

The protruding portion 117 extends from the base portion 115 in adirection opposite to the wiring layer 104. The protruding portion 117extends in the transverse direction along the major surface of the baseelectrode layer 103 and protrudes to the region outside the baseelectrode layer 103. The protruding portion 117 faces the first majorsurface 207 in the normal direction of the first major surface 207 atthe region outside the base electrode layer 103. The protruding portion117 defines a space 118 together with the first major surface 207 and aside surface of the base electrode layer 103. The space 118 is recessedtoward the side of the base electrode layer 103.

The bump structure 106 of each of the wiring structure bodies 101 isformed on the first pad portion 224 of the corresponding wiring layer104. The bump structure 106 each includes a UBM layer 119 and anelectroconductive bonding material 120 stacked in this order from theside of the wiring layer 104.

The UBM layer 119 is formed inside the first pad opening 226 of theinsulation layer 105. The UBM layer 119 includes a first electrode layer121 and a second electrode layer 122 stacked in this order from the sideof the wiring layer 104. The electroconductive bonding material 120 mayinclude a portion positioned inside the first pad opening 226 and aportion positioned outside the first pad opening 226. Theelectroconductive bonding material 120 may cover a major surface of theinsulation layer 105 outside the first pad opening 226.

The plurality of electrode bodies 204 (four in the preferred embodiment)are each formed on the second pad portion 225 of the correspondingwiring layer 104. The electrode bodies 204 are formed in a block shapeor in a pillar shape. The electrode body 204 has a single layerstructure which includes a copper layer (more specifically, a copperplating layer).

Each of the electrode bodies 204 has a first electrode surface 228 onone side, a second electrode surface 229 on the other side and anelectrode side surface 230 which connects the first electrode surface228 and the second electrode surface 229. The second electrode surface229 of each of the electrode bodies 204 is bonded to the second padportion 225 of the corresponding wiring layer 104. The electrode body204 may overlap with the insulation layer 105.

The chip component 203 is disposed on the first major surface 207 of theinterposer 202. The chip component 203 includes a chip main body 231formed in a rectangular parallelepiped shape. The chip main body 231 hasa mounting surface 232 on one side, a non-mounting surface 233 on theother side and a chip side surface 234 which connects the mountingsurface 232 and the non-mounting surface 233. The non-mounting surface233 is free of an electrode.

The chip main body 231 may include at least any one of silicon, anitride semiconductor material (for example, gallium nitride), an oxidesemiconductor material (for example, gallium oxide), silicon oxide,silicon nitride and ceramic. The chip main body 231 includes afunctional device. The chip main body 231 may be a discrete device whichis made up of a single functional device. The chip component 203 may bean integrated circuit device having multiple functional devices.

The chip component 203 includes a plurality of chip terminal electrodes235 (four in the preferred embodiment) formed on the mounting surface232. The plurality of chip terminal electrodes 235 are electricallyconnected to the functional devices. The mounting surface 232 may becovered with an insulation layer. In the insulation layer, there may beformed a wiring (wiring layer) which is electrically connected to thechip terminal electrode 235 and the functional device. In this case, theplurality of chip terminal electrodes 235 may protrude outside from theinsulation layer.

The chip component 203 is disposed over the first major surface 207 in aposture that the mounting surface 232 faces the interposer 202. Theplurality of chip terminal electrodes 235 are electrically connected tothe first pad region 221 of the wiring layer 104 through thecorresponding bump structure 106 (electroconductive bonding material120).

The sealing insulation layer 205 fills the space 118 on the first majorsurface 207, thereby sealing the plurality of wiring structure bodies101, the chip component 203 and the plurality of electrode bodies 204.The sealing insulation layer 205 includes a sealing major surface 241and a sealing side surface 242.

The sealing major surface 241 faces the first major surface 207. Thesealing major surface 241 is formed so as to be substantially parallelto the first major surface 207 (second major surface 208). The sealingside surface 242 extends toward the interposer 202 from a peripheraledge portion of the sealing major surface 241.

The sealing side surface 242 is connected to the side surface 209 of theinterposer 202 without any difference in level. The sealing side surface242 and the side surface 209 form one flat surface which extendscontinuously. This flat surface is formed by one ground surface. Thatis, the sealing side surface 242 is formed so as to be flush with theside surface 209.

The sealing major surface 241 is connected to the first electrodesurface 228 of each of the electrode bodies 204 without any differencein level. The sealing major surface 241 forms one continuously extendingflat surface with the first electrode surface 228 of each of theelectrode bodies 204. More specifically, the sealing major surface 241forms one ground surface with the first electrode surface 228 of each ofthe electrode bodies 204. That is, the sealing major surface 241 isformed so as to be flush with the first electrode surface 228 of each ofthe electrode bodies 204.

The plurality of external terminals 206 (four in the preferredembodiment) are each formed on the first electrode surface 228 of thecorresponding electrode body 204. Each of the external terminals 206 mayinclude an overlap portion which covers the sealing major surface 241.Each of the external terminals 206 may have a stacked-layer structurewhich includes a plurality of electrode layers. Each of the externalterminals 206 may have a stacked-layer structure which includes an Nilayer, a Pd layer and an Au layer stacked in this order from the firstelectrode surface 228-side of the electrode body 204.

As described so far, according to the electronic component 201, thewiring structure body 101 is interposed between the first major surface207 of the interposer 202 and the mounting surface 232 of the chipcomponent 203. The wiring structure body 101 includes the insulationlayer 105 which is formed on a peripheral edge portion of the baseelectrode layer 103 so as to protrude to a region outside the baseelectrode layer 103 from above the base electrode layer 103. The wiringstructure body 101 also includes the electroconductive bonding material120 which is formed on the wiring layer 104. Thereby, the moltenelectroconductive bonding material 120 can be prevented from wetting andspreading by the insulation layer 105. It is, thus, possible to preventthe electroconductive bonding material 120 from outflowing.

More specifically, the insulation layer 105 covers the wiring layer 104and has the first pad opening 226 which exposes the first pad region 221of the wiring layer 104. Inside the first pad opening 226, there isformed the bump structure 106 which includes the electroconductivebonding material 120. Thereby, the electroconductive bonding material120 can be prevented from making contact with the wiring layer 104.Thus, it is possible to appropriately prevent the moltenelectroconductive bonding material 120 from outflowing by the insulationlayer 105.

Further, the base electrode layer 103 is positioned at a region furtherinside than the insulation layer 105. Therefore, even if the moltenelectroconductive bonding material 120 oozes outside the insulationlayer 105, the electroconductive bonding material 120 can travel to thebase electrode layer 103 at the region further inside than theinsulation layer 105. Thereby, it is possible to prevent theelectroconductive bonding material 120 from outflowing to a regionoutside the insulation layer 105.

Further, according to the electronic component 201, the space 118 formedat a region between the protruding portion 117 of the insulation layer105 and the first major surface 207 of the interposer 202 is sealed bythe sealing insulation layer 205. Thereby, where the moltenelectroconductive bonding material 120 is present at the space 118, theelectroconductive bonding material 120 can be sealed inside the space118. It is, thereby, possible to appropriately prevent the moltenelectroconductive bonding material 120 from outflowing.

In the preferred embodiment, a description has been given of an examplethat the electronic component 201 includes the external terminal 206.However, the electronic component 201 may be free of the externalterminal 206. In this case, the first electrode surface 228 of each ofthe electrode bodies 204 may be formed as an external terminal.

FIG. 32 is a plan view which shows an electronic component 251 accordingto the twelfth preferred embodiment of the present invention. FIG. 33 isa cross-sectional view which is taken along line XXXIII-XXXIII shown inFIG. 32. In the following, structures corresponding to the structures inthe electronic component 201 (refer to FIG. 30 and FIG. 31) will begiven the same reference signs, and a description thereof is omitted.

With reference to FIG. 32 and FIG. 33, there is formed a recess portion252 which is recessed toward the side of a second major surface 208 on afirst major surface 207 of an interposer 202. The second major surface208 of the interposer 202 is formed to be flat.

The recess portion 252 is formed at a center portion of the first majorsurface 207 to be spaced inwardly from a side surface 209 of theinterposer 202 in plan view. The recess portion 252 is formed in aquadrangle shape which has four sides substantially parallel to therespective four sides of the interposer 202 in plan view.

The recess portion 252 is not limited to be formed in a quadrangle shapebut may be formed in any given planar shape. The recess portion 252 maybe formed in a triangular shape, a hexagonal shape, a circular shape oran elliptical shape in plan view. The recess portion 252 may becommunicatively connected to the side surface 209 of the interposer 202.

In the first major surface 207, there is formed a low region 253, a highregion 254 and a connection portion 255 by the recess portion 252. Thelow region 253 is made up of a bottom portion of the recess portion 252.The high region 254 is made up of a region around the recess portion252. The connection portion 255 connects the low region 253 and the highregion 254.

The low region 253 is formed in a quadrangle shape having four sidessubstantially parallel to the respective four sides of the interposer202 in plan view. The high region 254 is formed in an endless shape(quadrangular annular shape) which surrounds the recess portion 252 inplan view. The connection portion 255 has an inclined surface which isinclined downward from the high region 254 to the low region 253.

That is, the recess portion 252 is formed in a tapered shape in which anopening is reduced in width from the high region 254 to the low region253 in a cross-sectional view. The previously described chip region 212is formed at the low region 253. The previously described outer region213 is formed at the high region 254.

A first pad region 221 of each of the wiring structure bodies 101 isformed at the low region 253. A second pad region 222 of each of thewiring structure bodies 101 is formed at the high region 254. A wiringregion 223 of each of the wiring structure bodies 101 is drawn around ina line shape at a region between the low region 253 and the high region254 so as to cross the connection portion 255.

In the preferred embodiment, an insulation layer 105 (protruding portion117) of each of the wiring structure bodies 101 faces the low region253, the high region 254 and the connection portion 255 in a normaldirection of the first major surface 207 at a region outside a baseelectrode layer 103.

A chip component 203 is disposed inside the recess portion 252. The chipcomponent 203 is disposed over the low region 253 in a posture that amounting surface 232 faces the low region 253. A chip terminal electrode235 of the chip component 203 is bonded to the first pad region 221 of awiring layer 104 through a corresponding bump structure 106(electroconductive bonding material 120).

The mounting surface 232 of the chip component 203 is positioned at aregion between the low region 253 and the high region 254. Anon-mounting surface 233 of the chip component 203 may protrude abovethe high region 254. The non-mounting surface 233 may be positioned at aregion between the low region 253 and the high region 254.

The mounting surface 232 and the non-mounting surface 233 have an areawhich is less than an area of the low region 253 in plan view. Theentirety of the mounting surface 232 faces the low region 253. That is,the chip component 203 is positioned at a region surrounded by aperipheral edge of the low region 253.

The mounting surface 232 and the non-mounting surface 233 may have anarea that exceeds an area of the low region 253 in plan view. In thiscase, the mounting surface 232 may face a portion of the low region 253and a portion of the connection portion 255.

In the preferred embodiment, the sealing insulation layer 205 fills therecess portion 252, thereby sealing the wiring structure body 101, thechip component 203 and the electrode body 204. The sealing insulationlayer 205 seals a space 118 at regions inside and outside the recessportion 252.

As described so far, the electronic component 251 is also able toprovide substantially the same technical effects as those described inthe electronic component 201.

FIG. 34 is a plan view which shows an electronic component 261 accordingto the thirteenth preferred embodiment of the present invention. FIG. 35is a cross-sectional view taken along line XXXV-XXXV shown in FIG. 34.The electronic component 261 is a component in which the previouslydescribed wiring structure body 161 (refer to FIG. 23 and FIG. 24) isincorporated. In the following, structures corresponding to thestructures in the wiring structure body 161 will be given the samereference signs, and some of descriptions including those on dimensions,etc., of each structure of the wiring structure body 161 will beomitted.

The electronic component 261 includes a sealing insulation layer 262, aplurality of wiring structure bodies 161, a chip component 203, a baseinsulation layer 162 and a plurality of terminal electrode layers 163.Each of the wiring structure bodies 161 includes a portion of thesealing insulation layer 262, a base electrode layer 103, a wiring layer104, an insulation layer 105, a bump structure 106, the base insulationlayer 162 and the terminal electrode layer 163.

The sealing insulation layer 262 seals the wiring structure body 161 andthe chip component 203. The sealing insulation layer 262 has a firstsealing major surface 263 on one side, a second sealing major surface264 on the other side and a sealing side surface 265 which connects thefirst sealing major surface 263 and the second sealing major surface264.

The first sealing major surface 263 and the second sealing major surface264 are formed in a quadrangle shape (more specifically, in arectangular shape) in plan view taken from their normal directions. Thesealing side surface 265 extends along a normal direction of the firstsealing major surface 263. The first sealing major surface 263 may be aground surface. The sealing side surface 265 may be a ground surface.The second sealing major surface 264 is not a ground surface.

A chip region 266 and an outer region 267 are set inside the sealinginsulation layer 262. The chip region 266 is a region at which the chipcomponent 203 is disposed. The chip region 266 is set at a centerportion of the sealing insulation layer 262 to be spaced from thesealing side surface 265 in plan view. The chip region 266 is set in aquadrangle shape in plan view. The outer region 267 is a region outsidethe chip region 266. The outer region 267 is set in an endless shape(quadrangular annular shape) which surrounds the chip region 266 in planview.

The plurality of wiring structure bodies 161 (four in the preferredembodiment) are disposed to be spaced from each other inside the sealinginsulation layer 262. The plurality of wiring structure bodies 161 areeach formed so as to extend over the chip region 266 and the outerregion 267. The plurality of wiring structure bodies 161 each include afirst pad region 268, a second pad region 269, and a wiring region 270.

The first pad region 268 of each of the wiring structure bodies 161 isformed at the chip region 266. Each of the first pad regions 268 isconnected to the chip component 203. In the preferred embodiment, thefirst pad regions 268 are each formed in a quadrangle shape in planview. The first pad regions 268 are not limited to be each formed in aquadrangle shape but may be each formed in any given planar shape.

The second pad region 269 of each of the wiring structure bodies 161 isformed at the outer region 267. The terminal electrode layer 163 isconnected to each second pad region 269. In the preferred embodiment,the second pad regions 269 are each formed in a quadrangle shape in planview. The second pad regions 269 are not limited to be each formed in aquadrangle shape but may be each formed in any given planar shapeincluding.

The wiring region 270 of each of the wiring structure bodies 161connects the first pad region 268 and the second pad region 269 whichcorrespond thereto. In the preferred embodiment, the wiring regions 270are each drawn around in a line shape at a region between the first padregion 268 and the second pad region 269 which correspond thereto. Thewiring regions 270 may be each drawn around in any mode.

The base electrode layer 103 of each of the wiring structure bodies 161has a planar shape corresponding to the first pad region 268, the secondpad region 269 and the wiring region 270. The base electrode layer 103has a stacked-layer structure which includes a first electrode layer 111and a second electrode layer 112 stacked in this order from the secondsealing major surface 264-side of the sealing insulation layer 262.

A side surface of the second electrode layer 112 may be formed so as tobe flush with a side surface of the first electrode layer 111. The sidesurface of the second electrode layer 112 may protrude outside inrelation to the side surface of the first electrode layer 111. The sidesurface of the second electrode layer 112 may be formed inside inrelation to the side surface of the first electrode layer 111.

An electrode surface 164 of the base electrode layer 103 is exposed fromthe second sealing major surface 264. The electrode surface 164 isformed so as to be flush with the second sealing major surface 264. Oneflat surface is formed by the electrode surface 164 and the secondsealing major surface 264. The electrode surface 164 or the secondsealing major surface 264 is not a ground surface.

The wiring layer 104 of each of the wiring structure bodies 161 isformed on the base electrode layer 103. The wiring layer 104 has aplanar shape corresponding to the first pad region 268, the second padregion 269 and the wiring region 270. The wiring layer 104 is formed tobe spaced inwardly from a peripheral edge portion of the base electrodelayer 103, so as to expose the peripheral edge portion of the baseelectrode layer 103.

The wiring layer 104 includes a first pad portion 271 (connectionportion) and a second pad portion 272. The first pad portion 271 isformed at the first pad region 268. The second pad portion 272 is formedat the second pad region 269.

The insulation layer 105 of each of the wiring structure bodies 161 isformed on the base electrode layer 103. The insulation layer 105 has aplanar shape corresponding to the first pad region 268, the second padregion 269 and the wiring region 270. The insulation layer 105 coversthe wiring layer 104 so as to expose the first pad portion 271. Thereby,a pad opening 273 is formed in the insulation layer 105.

The insulation layer 105 protrudes to a region outside the baseelectrode layer 103 from above the peripheral edge portion of the baseelectrode layer 103. The insulation layer 105 protrudes in a transversedirection of a major surface of the base electrode layer 103. Morespecifically, the insulation layer 105 includes a base portion 115, acovering portion 116 and a protruding portion 117.

The base portion 115 is formed on the peripheral edge portion of thebase electrode layer 103. The covering portion 116 extends from the baseportion 115 toward above the wiring layer 104 and demarcates the padopening 273. The protruding portion 117 extends from the base portion115 in a direction opposite to the wiring layer 104. The protrudingportion 117 extends in the transverse direction along the major surfaceof the base electrode layer 103 and protrudes to a region outside thebase electrode layer 103. The protruding portion 117 forms a stepportion 165 between itself and a side surface of the base electrodelayer 103.

The bump structure 106 of each of the wiring structure bodies 161 isformed on the first pad portion 271 of the corresponding wiring layer104. The bump structure 106 includes a UBM layer 119 and anelectroconductive bonding material 120 stacked in this order from theside of the wiring layer 104.

The UBM layer 119 is formed inside the pad opening 273 of the insulationlayer 105. The UBM layer 119 includes a first electrode layer 121 and asecond electrode layer 122 stacked in this order from the side of thewiring layer 104. The electroconductive bonding material 120 may includea portion positioned inside the pad opening 273 and a portion outsidethe pad opening 273. The electroconductive bonding material 120 maycover a major surface of the insulation layer 105 outside the padopening 273.

The chip component 203 is disposed at the chip region 266 inside thesealing insulation layer 262. The chip component 203 is connected toeach of the wiring structure bodies 161 in a posture that the mountingsurface 232 faces the second sealing major surface 264. The chipterminal electrode 235 of the chip component 203 is bonded to the firstpad region 268 of the wiring layer 104 through the corresponding bumpstructure 106 (electroconductive bonding material 120).

The sealing insulation layer 262 covers a step portion 165 and seals thewiring structure body 161 and the chip component 203 so as to expose theelectrode surface 164 of the base electrode layer 103. A portion whichcovers the step portion 165 in the sealing insulation layer 262 forms astopper portion which prevents the insulation layer 105 from falling offfrom the sealing insulation layer 262.

The base insulation layer 162 covers the plurality of electrode surfaces164. The base insulation layer 162 further covers the second sealingmajor surface 264. More specifically, the base insulation layer 162collectively covers flat surfaces which are formed by the plurality ofelectrode surfaces 164 and the second sealing major surface 264. Thebase insulation layer 162 faces the protruding portion 117 of theinsulation layer 105 with the sealing insulation layer 262 (stopperportion) interposed therebetween. It is, thereby, possible toappropriately prevent the insulation layer 105 from falling off.

In the base insulation layer 162, there are formed a plurality of lowerpad openings 274 (four in the preferred embodiment) which expose theelectrode surface 164 of the base electrode layer 103. The plurality oflower pad openings 274 expose any given region of the correspondingelectrode surface 164 as a pad portion.

More specifically, the lower pad opening 274 is formed at a region whichdoes not overlap with the bump structure 106 in plan view. Still morespecifically, the lower pad opening 274 is formed in the correspondingsecond pad region 269. That is, the lower pad opening 274 exposes theelectrode surface 164 at the corresponding second pad region 269.

The plurality of terminal electrode layers 163 (four in the preferredembodiment) penetrate through the base insulation layer 162 and areconnected to the electrode surface 164 of the corresponding baseelectrode layer 103. More specifically, the plurality of terminalelectrode layers 163 are formed inside the corresponding lower padopenings 274. That is, the plurality of terminal electrode layers 163are formed at a region which does not overlap with the bump structure106 in plan view.

The plurality of terminal electrode layer 163 are electrically connectedto the second pad portions 272 of the wiring layer 104 through thecorresponding base electrode layer 103. The plurality of terminalelectrode layers 163 are formed as external terminal electrodes whichare to be connected externally.

The plurality of terminal electrode layers 163 protrude from a majorsurface of the base insulation layer 162 in a direction opposite to thebase electrode layer 103. The plurality of terminal electrode layers 163may have an overlap portion which covers the major surface of the baseinsulation layer 162. The plurality of terminal electrode layers 163 mayhave a stacked-layer structure including an Ni layer, a Pd layer and anAu layer formed in this order from the side of the base electrode layer103.

As described so far, the electronic component 261 is also able toprovide substantially the same technical effects as those described inthe electronic component 201.

FIG. 36 is a cross-sectional view of a region corresponding to thatshown in FIG. 31 and is a cross-sectional view which shows an electroniccomponent 281 according to the fourteenth preferred embodiment of thepresent invention. The electronic component 281 is different from theelectronic component 201 in that it includes a plurality of wiringstructure bodies 141 (refer to FIG. 19 and FIG. 20) in place of theplurality of wiring structure bodies 101. In the following, structurescorresponding to the structures in the electronic component 201 will begiven the same reference signs, and a description thereof is omitted.

With reference to FIG. 36, in the preferred embodiment, a secondelectrode layer 112 of a base electrode layer 103 protrudes to a regionoutside a first electrode layer 111 from above the first electrode layer111. The second electrode layer 112 protrudes in a transverse directionalong a major surface of the first electrode layer 111. The secondelectrode layer 112 faces a first major surface 207 in a normaldirection of the first major surface 207 at the region outside the firstelectrode layer 111.

More specifically, the second electrode layer 112 includes an electrodebase portion 142 and an electrode protruding portion 143. The electrodebase portion 142 covers the first electrode layer 111. The electrodeprotruding portion 143 extends from the electrode base portion 142 to aside opposite to the first electrode layer 111.

The electrode protruding portion 143 extends in the transverse directionalong the major surface of the first electrode layer 111 and protrudesto the region outside the first electrode layer 111. The electrodeprotruding portion 143 faces the first major surface 207 in the normaldirection of the first major surface 207 at the region outside the firstelectrode layer 111. The electrode protruding portion 143 defines afirst space 144 together with the first major surface 207 and a sidesurface of the first electrode layer 111.

A wiring layer 104 is formed on the base electrode layer 103, coveringcollectively the electrode base portion 142 and the electrode protrudingportion 143 of the second electrode layer 112. More specifically, thewiring layer 104 includes a wiring base portion 145 and a wiringprotruding portion 146.

The wiring base portion 145 covers the electrode base portion 142 of thesecond electrode layer 112. The wiring protruding portion 146 covers theelectrode protruding portion 143 of the second electrode layer 112. Aside surface of the wiring layer 104 is connected to a side surface ofthe second electrode layer 112 without any difference in level.

The wiring layer 104 may protrude to a region outside the secondelectrode layer 112 from above the second electrode layer 112. Thewiring layer 104 may protrude in a transverse direction along a majorsurface of the second electrode layer 112. The wiring layer 104 may facethe first major surface 207 in the normal direction of the first majorsurface 207 at the region outside the second electrode layer 112. A stepportion may be formed between the side surface of the wiring layer 104and the side surface of the second electrode layer 112.

An insulation layer 105 is formed on the wiring layer 104. Theinsulation layer 105 protrudes to a region outside the wiring layer 104from above the wiring layer 104. The insulation layer 105 protrudes in atransverse direction along a major surface of the wiring layer 104. Theinsulation layer 105 faces the first major surface 207 in the normaldirection of the first major surface 207 at the region outside thewiring layer 104. The insulation layer 105 exposes the side surface ofthe wiring layer 104.

More specifically, the insulation layer 105 includes an insulating baseportion 147 and an insulating protruding portion 148. The insulatingbase portion 147 covers the wiring base portion 145 of the wiring layer104. The insulating protruding portion 148 covers the wiring protrudingportion 146 of the wiring layer 104.

The insulating protruding portion 148 extends in the transversedirection along the major surface of the wiring layer 104 and protrudesto the region outside the wiring layer 104. The insulating protrudingportion 148 faces the first major surface 207 in the normal direction ofthe first major surface 207 at the region outside the wiring layer 104.The insulating protruding portion 148 defines a second space 149together with the first major surface 207 and the side surface of thewiring layer 104. The second space 149 is recessed toward the side ofthe wiring layer 104. The second space 149 is communicatively connectedto the first space 144.

A bump structure 106 is formed inside a first pad opening 226 formed inthe insulation layer 105. The first pad opening 226 exposes the wiringbase portion 145 of the wiring layer 104. Thereby, the bump structure106 is connected to the wiring base portion 145 of the wiring layer 104.

A sealing insulation layer 205 seals the wiring structure body 141, achip component 203 and an electrode body 204 on the first major surface207. The sealing insulation layer 205 enters into the first space 144and the second space 149.

As described so far, the electronic component 281 is also able toprovide substantially the same technical effects as those described inthe electronic component 201.

FIG. 37 is a cross-sectional view of a region corresponding to thatshown in FIG. 31 and is a cross-sectional view which shows an electroniccomponent 291 according to the fifteenth preferred embodiment of thepresent invention. The electronic component 291 is different from theelectronic component 281 in that it includes a wiring structure body 151(refer to FIG. 22 and FIG. 23) in place of the wiring structure body141. In the following, structures corresponding to the structures in theelectronic component 281 will be given the same reference signs, and adescription thereof is omitted.

With reference to FIG. 37, in the preferred embodiment, an insulationlayer 105 is free of an insulating protruding portion 148. Theinsulation layer 105 is formed at a region further inside than aperipheral edge portion of a wiring layer 104. The insulation layer 105covers at least a wiring base portion 145 of the wiring layer 104. Theinsulation layer 105 may cover a portion of a wiring protruding portion146 of the wiring layer 104.

A recess portion 152 which is recessed toward the side of a baseelectrode layer 103 is formed at an exposed portion which is exposedfrom the insulation layer 105 on a major surface of the wiring layer104. The recess portion 152 may be connected to a side surface of theinsulation layer 105 without any difference in level.

As described so far, the electronic component 291 is also able toprovide substantially the same technical effects as those described inthe electronic component 201.

FIG. 38 is a cross-sectional view of a region corresponding to thatshown in FIG. 33 and is a cross-sectional view which shows an electroniccomponent 301 according to the sixteenth preferred embodiment of thepresent invention. The electronic component 301 is different from theelectronic component 251 in that it includes a wiring structure body 141in place of the wiring structure body 101. In the following, structurescorresponding to the structures in the electronic component 251 will begiven the same reference signs, and a description thereof is omitted.

With reference to FIG. 38, in the preferred embodiment, a secondelectrode layer 112 of a base electrode layer 103 protrudes to a regionoutside a first electrode layer 111 from above the first electrode layer111. The second electrode layer 112 protrudes in a transverse directionalong a major surface of the first electrode layer 111. The secondelectrode layer 112 faces a first major surface 207 (a low region 253, ahigh region 254 and a connection portion 255) in a normal direction ofthe first major surface 207 at the region outside the first electrodelayer 111.

More specifically, the second electrode layer 112 includes an electrodebase portion 142 and an electrode protruding portion 143. The electrodebase portion 142 covers the first electrode layer 111. The electrodeprotruding portion 143 extends from the electrode base portion 142 to aside opposite to the first electrode layer 111.

The electrode protruding portion 143 extends in the transverse directionof the major surface of the first electrode layer 111 and protrudes tothe region outside the first electrode layer 111. The electrodeprotruding portion 143 faces the first major surface 207 (the low region253, the high region 254 and the connection portion 255) in the normaldirection of the first major surface 207 at the region outside the firstelectrode layer 111. The electrode protruding portion 143 defines afirst space 144 together with the first major surface 207 and a sidesurface of the first electrode layer 111. The first space 144 isrecessed toward the side of the first electrode layer 111.

A wiring layer 104 is formed on the base electrode layer 103. The wiringlayer 104 covers collectively the electrode base portion 142 and theelectrode protruding portion 143 of the second electrode layer 112. Morespecifically, the wiring layer 104 includes a wiring base portion 145and a wiring protruding portion 146.

The wiring base portion 145 covers the electrode base portion 142 of thesecond electrode layer 112. The wiring protruding portion 146 covers theelectrode protruding portion 143 of the second electrode layer 112. Aside surface of the wiring layer 104 may be connected to a side surfaceof the second electrode layer 112 without any difference in level.

The wiring layer 104 may protrude to a region outside the secondelectrode layer 112 from above the second electrode layer 112. Thewiring layer 104 may protrude in a transverse direction along a majorsurface of the second electrode layer 112. The wiring layer 104 may facethe first major surface 207 (the low region 253, the high region 254 andthe connection portion 255) in the normal direction of the first majorsurface 207 at the region outside the second electrode layer 112. A stepportion may be formed between the side surface of the wiring layer 104and the side surface of the second electrode layer 112.

An insulation layer 105 is formed on the wiring layer 104. Theinsulation layer 105 protrudes to a region outside the wiring layer 104from above the wiring layer 104. The insulation layer 105 protrudes in atransverse direction along a major surface of the wiring layer 104. Theinsulation layer 105 faces the first major surface 207 (the low region253, the high region 254 and the connection portion 255) in the normaldirection of the first major surface 207 at the region outside thewiring layer 104. The insulation layer 105 exposes the side surface ofthe wiring layer 104.

More specifically, the insulation layer 105 includes an insulating baseportion 147 and an insulating protruding portion 148. The insulatingbase portion 147 covers the wiring base portion 145 of the wiring layer104. The insulating protruding portion 148 covers the wiring protrudingportion 146 of the wiring layer 104.

The insulating protruding portion 148 extends in the transversedirection along the major surface of the wiring layer 104 and protrudesto the region outside the wiring layer 104. The insulating protrudingportion 148 faces the first major surface 207 (the low region 253, thehigh region 254 and the connection portion 255) in the normal directionof the first major surface 207 at the region outside the wiring layer104. The insulating protruding portion 148 defines a second space 149together with the first major surface 207 and the side surface of thewiring layer 104. The second space 149 is recessed toward the side ofthe wiring layer 104. The second space 149 is communicatively connectedto the first space 144.

A bump structure 106 is formed inside a first pad opening 226 formed onthe insulation layer 105. The first pad opening 226 exposes the wiringbase portion 145 of the wiring layer 104. Thereby, the bump structure106 is connected to the wiring base portion 145 of the wiring layer 104.

A sealing insulation layer 205 fills a recess portion 252, therebysealing the wiring structure body 141, a chip component 203 and anelectrode body 204. The sealing insulation layer 205 enters into thefirst space 144 and the second space 149 inside and outside the recessportion 252.

As described so far, the electronic component 301 is also able toprovide substantially the same technical effects as those described inthe electronic component 251.

FIG. 39 is a cross-sectional view of a region corresponding to thatshown in FIG. 33 and is a cross-sectional view which shows an electroniccomponent 311 according to the seventeenth preferred embodiment of thepresent invention. The electronic component 311 is different from theelectronic component 251 in that it includes a wiring structure body 151(refer to FIG. 22 and FIG. 23) in place of the wiring structure body101. In the following, structures corresponding to the structures in theelectronic component 251 will be given the same reference signs, and adescription thereof is omitted.

In the preferred embodiment, an insulation layer 105 is free of aninsulating protruding portion 148. The insulation layer 105 is formed ata region further inside than a peripheral edge portion of a wiring layer104. The insulation layer 105 covers at least a wiring base portion 145of the wiring layer 104. The insulation layer 105 may cover a portion ofa wiring protruding portion 146 of the wiring layer 104.

There is formed a recess portion 152 which is recessed toward the sideof a base electrode layer 103 at an exposed portion which is exposedfrom the insulation layer 105 on a major surface of the wiring layer104. The recess portion 152 may be connected to a side surface of theinsulation layer 105 without any difference in level.

As described so far, the electronic component 311 is also able toprovide substantially the same technical effects as those described inthe electronic component 251.

FIG. 40 is a cross-sectional view of a region corresponding to thatshown in FIG. 35 and is a cross-sectional view which shows an electroniccomponent 321 according to the eighteenth preferred embodiment of thepresent invention. The electronic component 321 is different from theelectronic component 261 in that it includes a wiring structure body 181(refer to FIG. 26 and FIG. 27) in place of the wiring structure body161. In the following, structures corresponding to the structures in theelectronic component 261 will be given the same reference signs, and adescription thereof is omitted.

With reference to FIG. 40, in the preferred embodiment, a secondelectrode layer 112 of a base electrode layer 103 protrudes to a regionoutside the base electrode layer 103 from above a first electrode layer111. The second electrode layer 112 protrudes in a transverse directionalong a major surface of the first electrode layer 111.

More specifically, the second electrode layer 112 includes an electrodebase portion 182 and an electrode protruding portion 183. The electrodebase portion 182 covers the first electrode layer 111. The electrodeprotruding portion 183 extends from the electrode base portion 182 to aside opposite to the first electrode layer 111. The electrode protrudingportion 183 extends in the transverse direction along the major surfaceof the first electrode layer 111 and protrudes to a region outside thefirst electrode layer 111. The electrode protruding portion 183 forms afirst step portion 184 between itself and a side surface of the firstelectrode layer 111.

A wiring layer 104 is formed on the base electrode layer 103. The wiringlayer 104 covers collectively the electrode base portion 182 and theelectrode protruding portion 183 of the second electrode layer 112. Morespecifically, the wiring layer 104 includes a wiring base portion 185and a wiring protruding portion 186.

The wiring base portion 185 covers the electrode base portion 182 of thesecond electrode layer 112. The wiring protruding portion 186 covers theelectrode protruding portion 183 of the second electrode layer 112. Aside surface of the wiring layer 104 may be connected to a side surfaceof the second electrode layer 112 without any difference in level.

The wiring protruding portion 186 may protrude to a region outside thesecond electrode layer 112 from above the second electrode layer 112.The wiring protruding portion 186 may protrude in a transverse directionalong a major surface of the second electrode layer 112. A step portionmay be formed between the side surface of the wiring layer 104 and theside surface of the second electrode layer 112.

An insulation layer 105 is formed on the wiring layer 104. Theinsulation layer 105 protrudes to a region outside the wiring layer 104from above the wiring layer 104. The insulation layer 105 protrudes in atransverse direction along a major surface of the wiring layer 104. Theinsulation layer 105 exposes the side surface of the wiring layer 104.More specifically, the insulation layer 105 has an insulating baseportion 187 and an insulating protruding portion 188.

The insulating base portion 187 covers the wiring base portion 185 ofthe wiring layer 104. The insulating protruding portion 188 covers thewiring protruding portion 186 of the wiring layer 104. The insulatingprotruding portion 188 extends in the transverse direction along themajor surface of the wiring layer 104 and protrudes to the regionoutside the wiring layer 104. The insulating protruding portion 188forms a second step portion 189 between itself and the side surface ofthe wiring layer 104.

A sealing insulation layer 262 seals a chip component 203 and the wiringstructure body 181. The sealing insulation layer 262 covers the firststep portion 184 and the second step portion 189 and exposes anelectrode surface 164 of the base electrode layer 103.

A portion which covers the first step portion 184 in the sealinginsulation layer 262 forms a first stopper portion which prevents thewiring layer 104 from falling off from the sealing insulation layer 262.A portion which covers the second step portion 189 in the sealinginsulation layer 262 forms a second stopper portion which prevents theinsulation layer 105 from falling off from the sealing insulation layer262.

A base insulation layer 162 faces the electrode protruding portion 183of the wiring layer 104 and the insulating protruding portion 188 of theinsulation layer 105 with the sealing insulation layer 262 (the firststopper portion and the second stopper portion) interposed therebetween.It is, thereby, possible to appropriately prevent the wiring layer 104and the insulation layer 105 from falling off.

As described so far, the electronic component 321 is also able toprovide substantially the same technical effects as those described inthe electronic component 261.

FIG. 41 is a cross-sectional view of a region corresponding to thatshown in FIG. 35 and is a cross-sectional view which shows an electroniccomponent 331 according to the nineteenth preferred embodiment of thepresent invention. The electronic component 331 is different from theelectronic component 261 in that it includes a wiring structure body 191(refer to FIG. 29) in place of the wiring structure body 161. In thefollowing, structures corresponding to the structures in the electroniccomponent 261 will be given the same reference signs, and a descriptionthereof is omitted.

With reference to FIG. 41, in the preferred embodiment, an insulationlayer 105 is free of an insulating protruding portion 188. Theinsulation layer 105 is formed at a region further inside than aperipheral edge portion of a wiring layer 104. The insulation layer 105covers at least a wiring base portion 185 of the wiring layer 104. Theinsulation layer 105 may cover a portion of a wiring protruding portion186 of the wiring layer 104.

A recess portion 192 which is recessed toward the side of a baseelectrode layer 103 is formed at an exposed portion which is exposedfrom the insulation layer 105 on a major surface of the wiring layer104. The recess portion 192 may be connected to a side surface of theinsulation layer 105 without any difference in level.

The wiring structure body 191 is manufactured by forming the insulationlayer 105 at a region further inside than the peripheral edge portion ofthe wiring layer 104 in the previously described step of forming theinsulation layer 105 (refer to FIG. 28B). The recess portion 192 isformed by removing a portion of the wiring layer 104 in the previouslydescribed step of removing the second electrode layer 112 (refer to FIG.28D).

As described so far, the electronic component 331 is also able toprovide substantially the same technical effects as those described inthe electronic component 261.

FIG. 42 is a plan view of a region corresponding to that shown in FIG.32 and is a plan view which shows an electronic component 341 accordingto the twentieth preferred embodiment of the present invention. Theelectronic component 341 is different from the previously describedelectronic component 251 in that each of wiring structure bodies 101includes a wiring region 223 which extends rectilinearly on an inclinedsurface of a connection portion 255. In the following, structurescorresponding to the structures in the electronic component 251 will begiven the same reference signs, and a description thereof is omitted.

With reference to FIG. 42, the wiring region 223 of each of the wiringstructure bodies 101 extends rectilinearly from a high region 254 towarda low region 253 on the inclined surface of the connection portion 255.That is, the wiring region 223 of each of the wiring structure bodies101 is free of a curve portion on the inclined surface of the connectionportion 255.

As described so far, the electronic component 341 is also able toprovide substantially the same technical effects as those described inthe electronic component 251. The electronic component 341 also includesthe wiring region 223 which extends rectilinearly on the inclinedsurface of the connection portion 255. According to the above-describedstructure, since the wiring region 223 is free of a curve portion at theconnection portion 255, it is possible to appropriately form the wiringstructure body 101.

That is, in the photographic exposure step of a mask 131 (refer to FIG.18B) which is conducted during the step of forming each of the wiringstructure bodies 101, since the connection portion 255 is inclineddownward, a distance between alight source and the low region 253 islarger than a distance between the light source and the high region 254.Therefore, there is a possibility that a position at which the mask 131is irradiated with light may misalign between the high region 254 andthe low region 253.

In particular, where the wiring region 223 has a curve portion at theconnection portion 255, due to misalignment in the irradiation positionof the mask 131 with light, the curve portion of the wiring region 223may not be appropriately formed. In order to avoid the above-describedproblem, the mask 131 is required to be irradiated with light understrictly controlled conditions, thus resulting in an increaseddifficulty in manufacture.

Therefore, in the electronic component 341, there is formed the wiringregion 223 which extends rectilinearly on the inclined surface of theconnection portion 255. It is, thereby, possible to minimize theinfluence resulting from misalignment in the irradiation position withlight. As a result, it is possible to avoid the increased difficulty inmanufacture.

The structure of the electronic component 341 is applicable to any andall modes in which the recess portion 252 is formed. The structure ofthe electronic component 341 shall not exclude a structure in which thewiring region 223 has a curve portion at the connection portion 255.

FIG. 43 is a plan view of a region corresponding to that shown in FIG.42 or a plan view which shows an electronic component 351 according tothe twenty-first preferred embodiment of the present invention. Theelectronic component 351 is different from the previously describedelectronic component 341 in that it includes a wiring region 223 whichis formed in a splayed shape (tapered shape) in plan view. In thefollowing, structures corresponding to the structures in the electroniccomponent 341 will be given the same reference signs, and a descriptionthereof is omitted.

With reference to FIG. 43, in the preferred embodiment, the wiringregion 223 of each of wiring structure bodies 101 is formed in a splayedshape (tapered shape) so that it extends rectilinearly on an inclinedsurface of a connection portion 255 in plan view and is also increasedin width from a high region 254 to a low region 253.

The wiring region 223 of each of the wiring structure bodies 101 crossesan inclined surface which extends along one direction (short-sidedirection of an interposer 202) at the connection portion 255. Thewiring region 223 of each of the wiring structure bodies 101 may have anoverlap portion 352 which covers an inclined surface adjacent to theinclined surface at the connection portion 255 and also extends along anintersecting direction (a long-side direction of the interposer 202)that intersects the one direction.

As described so far, the electronic component 351 is also able toprovide substantially the same technical effects as those described inthe electronic component 341. Further, according to the wiring region223 which is formed in a splayed shape (tapered shape), a wiring areacan be increased. It is, therefore, possible to further reduce theinfluence resulting from misalignment in the irradiation position withlight. Further, according to the wiring region 223 formed in a splayedshape (tapered shape), wiring resistance can be reduced within a limitedarea. The structure of the electronic component 341 is applicable to anyand all modes in which the recess portion 252 is formed.

As above, a description has been given of the fifth to the twenty-firstpreferred embodiments of the present invention. The present inventioncan be carried out in still other modes.

For example, the bump structure 106 according to the previouslydescribed fifth to twenty-first preferred embodiments may have astructure shown in FIG. 44. FIG. 44 is a cross-sectional view whichshows the first modified example of the bump structure 106 shown in FIG.17. In the following, structures corresponding to the structures in thebump structure 106 shown in FIG. 17 will be given the same referencesigns, and a description thereof is omitted.

With reference to FIG. 44, the bump structure 106 may include a UBMlayer 119 that has a single layer structure made up of an electrodelayer 400. The electrode layer 400 may include titanium. The bumpstructure 106 shown in FIG. 44 is applicable to all the fifth to thetwenty-first preferred embodiments.

Further, the bump structure 106 according to the previously describedfifth to twenty-first preferred embodiments may have a structure shownin FIG. 45. FIG. 45 is a cross-sectional view which shows the secondmodified example of the bump structure 106 shown in FIG. 17. In thefollowing, structures corresponding to the structures in the bumpstructure 106 shown in FIG. 17 will be given the same reference signs,and a description thereof is omitted.

With reference to FIG. 45, the bump structure 106 may include a UBMlayer 119 having a stacked-layer structure which includes a firstelectrode layer 401, a second electrode layer 402 and a third electrodelayer 403 that are stacked in this order from the side of a wiring layer104. The first electrode layer 401 may include copper. The secondelectrode layer 402 may include titanium. The third electrode layer 403may include copper. The bump structure 106 shown in FIG. 45 isapplicable to all the fifth to the twenty-first preferred embodiments.

Further, the bump structure 106 according to the previously describedfifth to twenty-first preferred embodiments may have a structure shownin FIG. 46. FIG. 46 is a cross-sectional view which shows the thirdmodified example of the bump structure 106 in FIG. 17. In the following,structures corresponding to the structures in the bump structure 106shown in FIG. 17 will be given the same reference signs, and adescription thereof is omitted.

With reference to FIG. 46, the bump structure 106 is free of anelectroconductive bonding material 120 but includes only a UBM layer119. The UBM layer 119 may have the mode shown in FIG. 17, the modeshown in FIG. 44 or the mode shown in FIG. 45. This structure iseffective in a case where a chip component 203 is provided with theelectroconductive bonding material 120. The bump structure 106 shown inFIG. 46 is applicable to all the fifth to the twenty-first preferredembodiments.

The present specification shall not restrict any mode of combination ofthe features shown in the fifth to the twenty-first preferredembodiments. The fifth to the twenty-first preferred embodiments can becombined in any given form or in any given mode among these embodiments.That is, there may be adopted such a mode that the features shown in thefifth to the twenty-first preferred embodiments are combined in anygiven form and in any given mode.

Hereinafter, examples of the features extracted from the fifth to thetwenty-first preferred embodiments are shown.

US2014252607A1 is given as a reference example. US2014252607A1 disclosesan electronic component which includes a substrate, a wiring formed onthe substrate and a semiconductor chip having an electrode which isconnected to the wiring through an electroconductive bonding material.

In the electronic component according to US2014252607A1, anelectroconductive bonding material is formed on the wiring. Therefore, amolten electroconductive bonding material may be wetted and spread overthe wiring, and the electroconductive bonding material may outflow to aregion outside the wiring. The electroconductive bonding material thathas outflowed to the region outside the wiring can cause an unexpectedfailure such as short circuit.

Thus, in the following, examples of features of a wiring structure bodyand those of an electronic component which can prevent anelectroconductive bonding material from outflowing are shown.

[A1] A wiring structure body which includes a base electrode layer, awiring layer which is formed on the base electrode layer so as to exposea peripheral edge portion of the base electrode layer, and an insulationlayer which is formed on the peripheral edge portion of the baseelectrode layer so as to protrude to a region outside the base electrodelayer from above the base electrode layer.

According to this wiring structure body, where an electroconductivebonding material is connected to the wiring layer, a moltenelectroconductive bonding material can be prevented from wetting andspreading by the insulation layer. It is, therefore, possible to preventthe electroconductive bonding material from outflowing.

[A2] The wiring structure body described in A1 in which the insulationlayer has a base portion that is formed on the peripheral edge portionof the base electrode layer and a protruding portion that extends fromthe base portion to a side opposite to the wiring layer and protrudesfurther outside than the peripheral edge portion of the base electrodelayer.

[A3] The wiring structure body described in A2 in which the insulationlayer has a covering portion that extends from the base portion towardabove the wiring layer and covers the wiring layer.

[A4] The wiring structure body described in anyone of A1 to A3 whichfurther includes an electroconductive bonding material formed on thewiring layer.

[A5] The wiring structure body described in any one of A1 to A4 whichfurther includes a support substrate having a major surface and in whichthe base electrode layer is formed on the major surface of the supportsubstrate and the insulation layer faces the major surface of thesupport substrate at the region outside the base electrode layer.

[A6] The wiring structure body described in A5 which further includes asealing insulation layer that is filled into a space formed between theinsulation layer and the major surface of the support substrate, therebysealing the insulation layer.

[A7] The wiring structure body described in A1 which further includes asealing insulation layer that covers a step portion formed by the baseelectrode layer and the insulation layer and seals the insulation layer.

[A8] The wiring structure body described in A7 which further includes abase insulation layer that covers the base electrode layer from a sideopposite to the insulation layer.

[A9] The wiring structure body described in A8 in which the baseinsulation layer covers the sealing insulation layer and faces the stepportion with the sealing insulation layer interposed therebetween.

[A10] The wiring structure body described in A8 or A9 which furtherincludes a terminal electrode layer that penetrates through the baseinsulation layer to be connected to the base electrode layer.

[A11] A wiring structure body which includes abase electrode layer, awiring layer that has a connection portion to be connected externallyand is formed on the base electrode layer so as to protrude to a regionoutside the base electrode layer from above the base electrode layer,and an insulation layer that covers the wiring layer so as to expose theconnection portion.

According to this wiring structure body, where an electroconductivebonding material is connected to the connection portion, a moltenelectroconductive bonding material can be prevented from wetting andspreading by the insulation layer. It is, therefore, possible to preventthe electroconductive bonding material from outflowing.

[A12] The wiring structure body described in A11 in which the wiringlayer has a wiring base portion that is formed on the base electrodelayer and a wiring protruding portion that extends from the wiring baseportion and protrudes to a region outside the base electrode layer.

[A13] The wiring structure body described in A11 or A12 which furtherincludes an electroconductive bonding material formed on the connectionportion of the wiring layer.

[A14] The wiring structure body described in any one of A11 to A13 whichfurther includes a support substrate having a major surface and in whichthe base electrode layer is formed on the major surface of the supportsubstrate, and the wiring layer faces the major surface of the supportsubstrate at the region outside the base electrode layer.

[A15] The wiring structure body described in A14 which further includesa sealing insulation layer that is filled into a space formed betweenthe wiring layer and the major surface of the support substrate, therebysealing the insulation layer.

[A16] The wiring structure body described in A11 which further includesa sealing insulation layer that covers a step portion formed by the baseelectrode layer and the wiring layer, and seals the wiring layer.

[A17] The wiring structure body described in A16 which further includesa base insulation layer that covers the base electrode layer from a sideopposite to the wiring layer.

[A18] The wiring structure body described in A17 in which the baseinsulation layer covers the sealing insulation layer and faces the stepportion with the sealing insulation layer interposed therebetween.

[A19] The wiring structure body described in A17 or A18 which furtherincludes a terminal electrode layer that is connected to the baseelectrode layer by penetrating through the base insulation layer.

[A20] An electronic component which includes a substrate that has amajor surface, a wiring structure body that is formed on the majorsurface of the substrate, an electroconductive bonding material that isformed on the wiring structure body, and a chip that is connected to thewiring structure body through the electroconductive bonding material,wherein the wiring structure body includes a base electrode layer thatis formed on the major surface of the substrate, a wiring layer that hasa connection portion that is formed on the base electrode layer so as toexpose a peripheral edge portion of the base electrode layer andconnected to the chip through the electroconductive bonding material,and an insulation layer that is formed on a peripheral edge portion ofthe base electrode layer so as to protrude to a region outside the baseelectrode layer from above the base electrode layer.

According to this electronic component, the wiring structure body isinterposed in a region between the substrate and the chip. The wiringstructure body includes the insulation layer formed on the peripheraledge portion of the base electrode layer so as to protrude to a regionoutside the base electrode layer from above the base electrode layer.Thereby, a molten electroconductive bonding material can be preventedfrom wetting and spreading by the insulation layer. It is, therefore,possible to prevent the electroconductive bonding material fromoutflowing.

[A21] An electronic component which includes a sealing insulation layer,a wiring structure body that is disposed insides the sealing insulationlayer, an electroconductive bonding material that is disposed inside thesealing insulation layer and is formed on the wiring structure body, anda chip that is disposed inside the sealing insulation layer and isconnected to the wiring structure body through the electroconductivebonding material, wherein the wiring structure body includes a baseelectrode layer which has a facing surface that faces the chip insidethe sealing insulation layer and an exposed surface that is positionedat a side opposite to the facing surface and exposed from the sealinginsulation layer, a wiring layer which has a connection portion that isinterposed between the base electrode layer and the chip, formed on thefacing surface of the base electrode layer so as to expose a peripheraledge portion of the base electrode layer and connected to the chipthrough the electroconductive bonding material, and an insulation layerwhich is interposed between the base electrode layer and the chip andformed on a peripheral edge portion of the base electrode layer so as toprotrude to a region outside the base electrode layer from above thebase electrode layer.

According to this electronic component, the wiring structure body andthe chip are sealed by the sealing insulation layer. The wiringstructure body includes the insulation layer which is formed on theperipheral edge portion of the base electrode layer so as to protrude toa region outside the base electrode layer from above the base electrodelayer. Thereby, a molten electroconductive bonding material can beprevented from wetting and spreading by the insulation layer. It is,therefore, possible to prevent the electroconductive bonding materialfrom outflowing.

[A22] The electronic component described in A20 or A21 in which theinsulation layer has a base portion that is formed on the peripheraledge portion of the base electrode layer and a protruding portion thatextends from the base portion to a side opposite to the wiring layer andprotrudes further outside than the peripheral edge portion of the baseelectrode layer.

[A23] The electronic component described in A22 in which the insulationlayer has a covering portion which extends from the base portion towardabove the wiring layer and covers the wiring layer so as to expose theconnection portion.

While preferred embodiments of the present invention have been describedabove, it is to be understood that variations and modifications will beapparent to those skilled in the art without departing from the scopeand spirit of the present invention. The scope of the present invention,therefore, is to be determined solely by the following claims.

What is claimed is:
 1. An electronic component comprising: a substratethat has a first major surface on one side and a second major surface onthe other side; a wiring layer that is formed on the first major surfaceof the substrate; a chip that has a mounting surface on one side and anon-mounting surface on the other side and is disposed on the firstmajor surface of the substrate in a posture that the mounting surfacefaces the first major surface of the substrate; a terminal electrodethat is formed on the mounting surface of the chip and is electricallyconnected to the wiring layer; an electrode body that is formed on thewiring layer to be spaced from the chip and is electrically connected tothe chip through the wiring layer; a sealing insulation layer that sealsthe chip and the electrode body on the first major surface of thesubstrate such as to expose the non-mounting surface and a portion ofthe electrode body; and a cover layer that is formed on the sealinginsulation layer such as to cover the non-mounting surface of the chipand expose the portion of the electrode body, wherein the cover layerhas a peripheral edge formed to be spaced from a peripheral edge of thesealing insulation layer and the electrode body such as to expose aperipheral edge portion of the sealing insulation layer and positionedat a region between the peripheral edge of the sealing insulation layerand the electrode body.
 2. The electronic component according to claim1, wherein the cover layer covers an entirety of the non-mountingsurface of the chip.
 3. The electronic component according to claim 1,wherein the cover layer includes an insulator.
 4. The electroniccomponent according to claim 1, wherein the non-mounting surface of thechip is a ground surface.
 5. The electronic component according to claim1, wherein the sealing insulation layer has an outer surface thatextends continuously from the non-mounting surface of the chip.
 6. Theelectronic component according to claim 1, wherein the cover layer has athickness that is equal to or less than a thickness of the sealinginsulation layer.
 7. The electronic component according to claim 1,wherein the cover layer has a thickness that is equal to or less than athickness of the chip.
 8. The electronic component according to claim 1,wherein the cover layer has a thickness which is 1 μm or more and 10 μmor less, from 10 μm or more and 20 μm or less, from 20 μm or more and 30μm or less, from 30 μm or more and 40 μm or less, or from 40 μm or moreand 50 μm or less.
 9. The electronic component according to claim 1,wherein the first major surface of the substrate includes a recessportion that is recessed toward the second major surface, and the chipis disposed inside the recess portion.
 10. The electronic componentaccording to claim 1, wherein the first major surface of the substrateincludes a low region made up of a bottom portion of a recess portionthat is recessed toward the second major surface, and a high region madeup of a region around the recess portion, and the chip is disposed atthe high region so as to cover the recess portion.
 11. The electroniccomponent according to claim 10, further comprising a lower chip that isdisposed inside the recess portion, wherein the sealing insulation layerseals the lower chip inside the recess portion.
 12. The electroniccomponent according to claim 1, wherein the first major surface of thesubstrate is made up of a flat surface.
 13. The electronic componentaccording to claim 1, wherein the cover layer partially covers theportion of the electrode body.
 14. An electronic component comprising: asubstrate that has a first major surface on one side and a second majorsurface on the other side; a wiring layer that is formed on the firstmajor surface of the substrate; a chip that has a mounting surface onone side and a non-mounting surface on the other side and is disposed onthe first major surface of the substrate in a posture that the mountingsurface faces the first major surface of the substrate; a terminalelectrode that is formed on the mounting surface of the chip and iselectrically connected to the wiring layer; an electrode body that isformed on the wiring layer to be spaced from the chip and iselectrically connected to the chip through the wiring layer; a sealinginsulation layer that seals the chip and the electrode body on the firstmajor surface of the substrate such as to expose the non-mountingsurface and a portion of the electrode body; and a cover layer that isformed on the sealing insulation layer such as to cover the non-mountingsurface of the chip and expose the portion of the electrode body,wherein the cover layer partially covers the portion of the electrodebody.